Method for establishing time sequence diagram in parallel based on geometrical information

Abstract

The invention provides a method for establishing a time sequence diagram in parallel based on geometrical information. The method comprises the following steps of conducting the geometrical block division on a circuit diagram according to geometrical characteristics of the circuit diagram; starting a plurality of processes, and establishing a temporary time sequence diagram in each geometric blockin parallel; and splicing the temporary time sequence diagrams established in the geometric blocks into a complete time sequence diagram. According to the method for establishing the time sequence diagram in parallel based on the geometrical information, a plurality of processes can be started to establish the time sequence diagram in parallel for the geometrical blocks, the method can be easilyimplemented by a distributed system, and the time for establishing the time sequence diagram in static time sequence analysis is greatly shortened.

Description

technical field [0001] The present invention relates to the technical field of electronic design automation (EDA), in particular to a method for building sequence diagrams in parallel based on geometric information. Background technique [0002] At different stages of integrated circuit design, it is necessary to check the timing of the design to ensure that the designed circuit can meet the predetermined timing requirements. Static Timing Analysis (STA) is stimulus-independent and enables fast and accurate measurements of circuit timing to measure circuit performance. [0003] Static timing analysis uses an exhaustive analysis method. It extracts all timing paths in the entire circuit, constructs timing diagrams, calculates the delay propagation of signals on the paths, and finds errors that violate timing constraints. [0004] The timing diagram mainly includes the logical nodes, connection relationships and main input and output ports of the timing path. Among them, th...

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Problems solved by technology

[0005] As the scale of integrated circuit design continues to increase, it takes a long time for traditional static timing analysis tools to establish all the timing diagrams of the entire circuit

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