A Distributed Static Timing Analysis Method

Abstract

A static timing analysis method based on distribution, comprising the following steps: establishing and grouping timing diagrams; finding the timing diagrams to be split in each group of timing diagrams, and splitting them into multiple timing subgraphs; finding each group of timing diagrams The timing diagram to be split is divided into multiple timing subgraphs; the design data of timing analysis is read for each group of timing diagrams in the new group; and the static timing analysis is performed in parallel for each group of timing diagrams in the new group. The distributed-based static timing analysis method of the present invention can greatly improve the efficiency of parallel calculation of the timing diagram after splitting the timing diagram compared with that before splitting.

Description

technical field [0001] The present invention relates to the technical field of electronic design automation (EDA), in particular to a distributed-based static timing analysis method. Background technique [0002] In the existing integrated circuit design, it is necessary to check the timing of the design at each different stage, so as to ensure that the designed circuit can meet the predetermined timing requirements. Static Timing Analysis (STA) is stimulus-independent and enables fast and accurate measurements of circuit timing to measure circuit performance. [0003] Static timing analysis uses an exhaustive analysis method. It extracts all timing paths in the entire circuit, constructs timing diagrams, calculates the delay propagation of signals on the paths, and finds errors that violate timing constraints. [0004] The timing diagram mainly includes the logical nodes, connection relationships and main input and output ports of the timing path. Among them, the logic n...

AI Technical Summary

Problems solved by technology

[0005] As the scale of integrated circuit design continues to increase, the timing diagram of the entire circuit is very complex, and there are many nodes on some timing paths, so it takes a long time to perform static timing analysis on the entire circuit

Images