Device and method for instruction scheduling

Abstract

The invention provides a device and a method for dynamically scheduling instructions transmitted from an operation queue to a reservation station in a microprocessor. The method comprises the following: a step of writing instructions, which is to set and then write the operand states of the decoded instructions on the basis of data correlation between the decoded instructions to be written into the operation queue and effective instructions in the operation queue, as well as instruction execution results which have been written back and are being written; a step of updating the operand states, which is to update the operand state of each instruction not transmitted on the basis of the data correlation between each instruction not transmitted and the instructions being written back of instruction execution results; a step of judging to-be-transmitted instructions, which is to judge whether the to-be-transmitted instructions with all operands ready exist on the basis of the operand state of each instruction not transmitted; and a step of transmitting instructions, which is to transmit the judged to-be-transmitted instructions to the reservation station when the reservation station has vacancies. Pipeline efficiency can be effectively improved by transmitting the instructions with the operands ready to the reservation station on the basis of the data correlation between the instructions.

Description

technical field [0001] The present invention relates to the architecture of the microprocessor, in particular to a device and method for dynamically dispatching instructions from the operation queue to the reservation station in the microprocessor. Background technique [0002] Modern microprocessors usually use pipeline technology to increase the processing speed of the microprocessor. Through pipeline technology, different instructions are executed in parallel at different stages to improve the performance of the processor. However, the data dependency between instructions will seriously affect the parallelism of instructions, thereby reducing the utilization rate of the pipeline and the performance of the processor. [0003] In order to solve the impact of data correlation between instructions on instruction parallelism, many microprocessors choose to use a pipeline structure that dynamically schedules instructions, such as the Tomasulo algorithm. The decoded instructio...

AI Technical Summary

Problems solved by technology

[0004] For the above technique of dynamically scheduling instructions, all instructions are decoded and written into the same operation queue, and different types of instructions are sequentially sent from the operation queue to different types of reservation stations. (Due to hardware overhead considerations, the number of items in the reservation station is generally not many), so that the number of operand-prepared instructions in the operation queue is theoretically more than that of the operand-prepared instructions in the reservation station. Therefore, there is the following problem: when the reservation station corresponding to the first instruction in the operation queue is in a saturated state for a long time (that is, there is no idle item in the reservation station), then the first instruction will always be kept in the operation queue without being deleted. Issue into a reservation station so that other instructions in the operation queue cannot be issued even if the reservation station corresponding to the operation queue has a free entry

Further, if an exception occurs in the memory access instruction at this time and many cycles are required to process the exception, the functional unit corresponding to the fixed-point instruction will be in an idle state at this time, which will obviously reduce the utilization rate of the pipeline and the performance of the processor

[0006] In addition, the above-mentioned technology for dynamically scheduling instructions still has a problem: when there is no idle item in the reservation station and the operand of the instruction in the reservation station is not ready, even if there is an instruction whose operand is ready in the operation queue, the cannot execute the command

In other words, even if the operand of the SUB instruction is ready, it cannot be executed, which will obviously lead to a decrease in pipeline efficiency

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