Pipeline scheduling method and device

Abstract

The invention discloses an assembly line scheduling device, which comprises three physical assembly lines, two mix buffers and a bus pipe bus, and is characterized in that the three physical assemblylines are logically divided into five assembly lines, and the five assembly lines respectively correspond to five stages of processing messages in a chip, i.e., a parse stage, a bridge stage, a routerstage, a post stage and an egress stage; the two mix buffers are used for scheduling different services and then sending the different services to the corresponding logic assembly lines; and each pipeline unit pipe, the mix buffer and the pdsrc are hung on the bus pipe bus and are used for completing the interaction among the pipeline units. According to the invention, various services are optimized in the aspect of assembly line processing length, and different services can correspond to different processing lengths, so that unnecessary processing is reduced; the pipe bus is used for replacing the original connection relationship among the members of the assembly line, so that the members of the assembly line are connected more flexibly, the expandability is very high, and the new requirements in the future can be met. The invention further provides a corresponding assembly line scheduling method.

Description

technical field [0001] The invention belongs to the technical field of semiconductor chips, and more specifically relates to a pipeline scheduling method and device. Background technique [0002] NP (network processor, network processor) pipeline technology is the core technology of network processors. The traditional NP pipeline is often determined by the physical pipeline length of the chip, and the length is generally fixed. It has nothing to do with the type of business and cannot be flexibly adapted. For business processing requirements, the forwarding delays of various services are basically the same, and the optimization of processing mainly depends on microcode application developers. In order to cope with the application requirements of massive connections and enhanced bandwidth in 5G networks, the traditional packet service processing pipeline is becoming more and more complex, and the main frequency design requirements are getting closer and closer to the limit of...

AI Technical Summary

Problems solved by technology

[0002] NP (network processor, network processor) pipeline technology is the core technology of network processors. The traditional NP pipeline is often determined by the physical pipeline length of the chip, and the length is generally fixed. It has nothing to do with the type of business and cannot be flexibly adapted. Business processing requirements, the forwarding delay of various services is basically the same, and the optimization of processing mainly depends on microcode application developers

In order to cope with the application requirements of massive connections and enhanced bandwidth in 5G networks, the traditional packet service processing pipeline is becoming more and more complex, and the main frequency design requirements are getting closer and closer to the limit of Moore's law realized by semiconductor physics. It is difficult for its architecture to meet the ultra-low latency in 5G networks at the same time requirements

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