60results about How to "Reduce wiring density" patented technology

In a method for designing a layout for an LSI, library data, which is information on a standard cell with an assigned parameter or parameters each indicating the probability of occurrence of violations of design rules at a pin connection point, is read into a library information read section in a global routing processing device. And in a global routing density processing section and a wire route determination processing section, the density of global routes that pass above a chip area divided into a plurality of portions in a grid pattern by a grid division processing section is set according to the parameters, so that the density of routes at pin connection points where the probability of occurrence of violations of design rules is high becomes low. Therefore, the global routing is carried out in such a manner that occurrence of violations of design rules at the pin connection points are prevented as much as possible.

The invention discloses an organic light emitting diode display array. According to the organic light emitting diode display array, through changing the time sequence control relationship and circuit connection relationship of organic light emitting diode pixel units, organic light emitting diode sub pixels of adjacent lines can share signals of scanning lines arranged in the middle of the two. On the premise of not reducing the performances of a pixel compensation circuit, wiring of N-1 scanning lines can be reduced for N lines of sub pixel unit arrays, wiring density can be greatly reduced, and the wiring space is saved.

A suspension board with circuit includes a conductive pattern on a top surface thereof. A folded-back portion that is capable of being folded back toward a back surface side is provided therein. At the circumference edge of the folded-back portion, a part of the circumference edge is continuous to the suspension board with circuit around the folded-back portion via a bent portion and the remaining portion of the circumference edge is disposed apart from the suspension board with circuit around the folded-back portion by a penetrating space that penetrates the suspension board with circuit in a thickness direction. The conductive pattern at least includes a top-surface-side terminal that is disposed on the top surface of the suspension board with circuit and a back-surface-side terminal that is disposed in the folded-back portion.

The invention relates to a manufacturing method for a printed circuit board, wherein manufacturing of a multi-layer high-density interconnected printed circuit board can be realized by using the one-time compressing method. The method comprises the following steps that: first daughter boards and second daughter boards are manufactured; the plurality of first daughter boards and daughter boards are superposed together and heating and pressurizing are carried out, and thus the first daughter boards and the second daughter boards are bonded together to form a multi-layer and multi-stage printed circuit board; conventional processes like mechanical drilling, hole metallization, and electroplating and the like are carried out on the multi-layer printed circuit board so as to complete the manufacturing of the printed circuit board. According to the invention, expansion and shrinkage as well as deformation of materials during the manufacturing process can be effectively controlled, thereby effectively improving alignment precision between the holes and between the hole and the graph; and the safe distances between the holes and between the hole and the graph are reduced from 20 mil to 8mil, thereby effectively improving the wiring density of the printed circuit board. Moreover, under the circumstances that the investment of the PCB manufacturer equipment is not increased, the yield of the high-density interconnected printed circuit board can be substantially improved and the manufacturing period of the product can be shortened.

The invention provides a kind of circuit board's structure and its preparation method, which includes: to form No.1 and No. 2 dielectric layer on the No. 1 and No. 2 loading plate, then separate one side of the No. 1 and No. 2 circuit layer that are formed on the No. 1 and No. 2 loading plate into one No. 3 dielectric layer and then laminate them, embed the No. 1 circuit layer into the position between the No. 1 dielectric layer and the No. 3 dielectric layer, embed the No. 2 circuit layer into the position between the No. 2 dielectric layer and No. 3 dielectric layer, and to form a No. 3 circuit layer on the outer surface of the No. 1 dielectric layer, form a No. 4 circuit layer on the outer surface of the No. 2 dielectric layer; the circuit board structure of the invention includes: sandwich layer plate, No. 3 circuit layer, No. 4 circuit layer; the circuit board structure of the invention and its preparation method enhances the wiring density for the circuitry of the circuit board, shortens the path for transmitting signal, improves the electric property quality of the circuit board, simplies the working procedures, shortens the time for all working procedures and reduces the cost for all working procedures, lessens the thcickness of circuit board, which meets the development trendancy of micromation.

The embodiment of the invention provides an array substrate, a preparing method of the array substrate and a display device and relates to the technical field of display. The wiring density of data leads in a densely-wired area can be reduced, and the probability of electrostatic discharge at a corner tip can be reduced. The array substrate comprises a display area and a peripheral area, wherein first data leads and at least two cascaded shifting register units are arranged in the peripheral area. The shifting register units are connected with grid lines in the display area through the first data leads. The minimum distance between every two adjacent first data leads is larger than or equal to a distance threshold value.

The invention discloses a self-alignment integrated package method of a high-density three-dimensional lamination layer, and aims to provides an integrated package method which employs a BGA welding ball as an interlayer mechanical support for multi-layer substrate self-alignment three-dimensional stack and also can be a signal interconnection passage among high-density layers. The self-alignmentintegrated package method is implemented according to the technical scheme that bonding pads are arranged on a lower surface of a top-layer substrate, an upper surface and a lower surface of an intermediate-layer substrate and an upper surface of a bottom-layer substrate and are used for welding micro BGA welding balls, the micro BGA welding balls are attached onto the upper surface of the intermediate-layer substrate and the upper surface of the bottom-layer substrate, the micro BGA welding balls on the upper surface of the intermediate-layer substrate are corresponding to the lower surface of the top-layer substrate, the micro BGA welding balls on the upper surface of the bottom-layer substrate are corresponding to the lower surface of the intermediate-layer substrate, vertical and interconnection rectangular array micro BGA ball welding is formed, a hollow square boss cavity box body is arranged at the peripheries outside an upper cavity surface of the intermediate-layer substrate 2and an upper cavity surface of the bottom-layer substrate 3, the cavity box body is stacked and placed in a backflow welding furnace by a tool, and self-alignment lamination layer welding is performed to form a package body.

There is provided a method for manufacturing a printed circuit board having an insulative board and a plurality of electroconductive pads arranged in a grid shape on the insulative board, the method comprising: a step for forming an electroconductive film on the insulative board; a step for forming a pattern on the electroconductive film so as to form the electroconductive pads, a lead wire connected to at least one of the electroconductive pads, and inter-pad wiring for electrically connecting each of the electroconductive pads not connected to the lead wire to any of the electroconductive pads connected to the lead wire, the inter-pad wiring being disposed between mutually adjacent electroconductive pads; a step for plating each of the electroconductive pads by immersing the insulative board in a plating bath and energizing each of the electroconductive pads through the lead wire; and a step for removing the inter-pad wiring.

An acceleration sensor includes a frame-shaped beam portion disposed above an XY substrate surface of a base in a floating state and a beam-portion supporting/fixing unit arranged to attach the beam portion to the base with support portions so as to be supported on two sides. The acceleration sensor also includes weight portions disposed above the XY substrate surface of the base in a floating state and connecting portions for attaching the weight portions to the beam portion in a cantilever state. The weight portions are movable in three axial directions including an X-axis direction, a Y-axis direction, and a Z-axis direction when the beam portion is deflected. The beam portion is provided with an X-axis-direction acceleration detection unit arranged to detect an acceleration in the X-axis direction, a Y-axis-direction acceleration detection unit arranged to detect an acceleration in the Y-axis direction, and a Z-axis-direction acceleration detection unit arranged to detect an acceleration in the Z-axis direction. The Z-axis-direction acceleration detection unit is disposed near proximal ends of Y-axis-direction extending portions of the beam portion, and the Y-axis-direction acceleration detection unit is disposed near distal ends of the Y-axis-direction extending portions.

Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.

In a linear conductor forming step, a wide portion having a relatively large line width and a narrow portion having a relatively small line width are formed in each of a plurality of linear conductors. In addition, in a multilayer board, in base material layers adjacent to each other in a stacking direction, the wide portion overlaps the narrow portion on the adjacent base material layer, and end portions of the wide portions at both sides of the narrow portion in a line width direction, in a planar view. The wide portions are disposed such that the end portions thereof overlap each other in the stacking direction and resistance of a fluid thermoplastic resin increases. The narrow portion is located between the wide portions in the stacking direction.

The invention discloses a display device, display system and manufacturing method. The display device comprises a display panel and a chip on film, wherein the chip on film comprises a driving chip, afirst electrode array, a second electrode array and a plurality of leads, the driving chip is provided with a plurality of chip pins; a plurality of chip pins are respectively led out by electrodes in the first electrode array; a second electrode array is used for providing a plurality of signal channels between the driving chip and the display panel; and the plurality of leads are respectively used for connecting the effective pins in the plurality of chip pins to the corresponding signal channels, so that the effective pins are electrically connected with the corresponding driving terminalson the display panel, when the plurality of chip pins comprise at least one idle pin and at least one effective pin, the leads, the effective pins and the driving terminals are the same in number. The chip of the display device comprises at least one idle pin, and the wiring density of the lead is reduced, so that the short circuit and electric leakage risks of the display device caused by overlarge wiring density are reduced, and the problem of increased coupling capacitance is avoided.

Disclosed herein is a device that includes: a plurality of first standard cells arranged on a semiconductor substrate in a first direction, each of the first standard cells including at least one field-effect transistor; and a first power supply wiring extending in the first direction along one end of the first standard cells in a second direction. The field-effect transistor including a gate electrode formed on a gate wiring layer. The first power supply wiring being formed on the gate wiring layer.

Provided is an optical module in which wiring density may be reduced to ensure isolation between lines to reduce crosstalk. A flexible printed circuit includes: dielectric layers; a first pattern facing portion including a first ground conductor pattern and a first wiring pattern electrically connected to an electric terminal, which are facing each other through the dielectric layer; and a second pattern facing portion including a second ground conductor pattern and a second wiring pattern electrically connected to the electric terminal, which are facing each other through the dielectric layer, the second pattern facing portion facing the first pattern facing portion, in which when the dielectric layer is bent along a portion between the first pattern facing portion and the second pattern facing portion, at least one of the first ground conductor pattern and the second ground conductor pattern is located between the first wiring pattern and the second wiring pattern.

A 3D memory device and a method of manufacture that same are disclosed. The 3D memory device includes a laminated structure including a plurality of stacked gate conductors and a plurality of interlayer insulating layers; A plurality of channel columns penetrating the laminated structure; A plurality of bit lines and a common source line located on a surface of the laminated structure, one end ofthe channel post being connected to a corresponding bit line of the plurality of bit lines and the other end being connected to the common source line in common; Wherein the plurality of bit lines andthe common source lines are staggered on a surface of the laminated structure. The 3D memory device adopts common source lines and bit lines interleaved on the surface of the 3D memory device stack structure, and the interleaved wiring can use the common source lines between the bit lines to isolate the common source lines and the bit lines, thereby reducing parasitic capacitance and parasitic resistance, improving storage density and access speed, and improving yield and reliability of the 3D memory device.

The invention relates to the field of phased-array antennas, in particular to a single-feed-point array combined circularly polarized phased-array antenna. The antenna comprises a first array combination and a second array combination, wherein the first array combination consists of 2*2 single-feed-point circularly polarized antenna units, and the 2*2 single-feed-point circularly polarized antennaunits rotate clockwise or anticlockwise around the center of the first array combination for 0 degree, 90 degrees, 180 degrees and 270 degrees orderly; the second array combination is composed of 2*2single-feed-point circularly polarized antenna units, and the second array combination is obtained by translating each antenna unit of the first array combination clockwise or anticlockwise by 90 degrees around the center of the first array combination. The phased-array antenna is formed by arranging a plurality of first array combinations and a plurality of second array combinations in a staggered mode in the transverse direction and the longitudinal direction. The single-feed-point array combined circular polarization phased array antenna of the present invention is used for solving the problems of narrow axial ratio bandwidth, large cross polarization radiation and the like in single-feed-point circular polarization design.

The invention provides a wiring structure of a sample detection pore plate, and the sample detection pore plate. The sample detection pore plate is provided with a substrate, a plurality of detectionelectrodes are disposed on the surface side of the substrate, each of the plurality of detection electrodes comprises a working electrode to which a voltage is applied and an opposite electrode for detecting and outputting a detection signal, the wiring structure comprises a power supply wiring for supplying power to the working electrode and a signal wiring for outputting the detection signal ofthe opposite electrode, and each of the power supply wiring and the signal wiring comprises a surface wiring portion disposed on the surface of the substrate, a back surface wiring portion disposed onthe back surface of the substrate, and a wiring penetrating portion for penetrating through the substrate and connecting the surface wiring portion with the back surface wiring portion. The wiring structure provided by the invention can reduce the wiring length on the surface side of the substrate, reduce the wiring density and improve the degree of freedom in the wiring design on the surface side and the back surface side of the substrate.