295 results about "Optical interconnect" patented technology

The invention provides a financial data analysis, identification and acquisition method and system. According to the method, firstly, a financial evolution graph is constructed based on cross-cycle financial revenue and expenditure data, multi-source heterogeneous financial data are integrated in real time through an optical interconnection storage device, time-space correlation characteristics are synchronously written in through a dynamic wavelength allocation protocol, and optical interconnection enhanced dynamic graph nodes are generated. A deviation early warning feature vector is generated by combining capital flow entropy change of an atlas node, after an atlas topology reconstruction rule is triggered, cross-department data consistency is verified through polarization state coding of an optical interconnection device, and policy effect lag parameters are extracted. And finally, correcting the weight of the atlas node based on a dynamic prediction mechanism, and outputting a cross-department financial traceability report. According to the technical scheme provided by the invention, through optical interconnection enhanced dynamic atlas and cross-department data fusion, the financial resource configuration abnormity monitoring capability is improved, and accurate traceability of a policy lag effect and a fund chain fracture risk is realized.

The invention relates to the technical field of semiconductor photoelectronics, and discloses a multi-physics field coupling silicon-based optical interconnection chip degradation model construction method and application, and the method comprises the steps: firstly constructing a multi-physics field coupling analysis model, and quantitatively representing the coupling relation of thermodynamics, optics, electricity and material aging through an inter-field coupling equation and a material aging dynamic model; simulating field distribution of a chip key area under multi-environment stress through finite element analysis, and extracting data; then historical degradation data is collected by combining an accelerated aging test and long-term operation monitoring, and a degradation parameter prediction model is established after data processing based on machine learning; and finally, inputting a finite element result and a prediction result into a material aging dynamic model, and finally forming a multi-physics field coupling degradation model. The problems that the prior art depends on a single physical field, degradation mechanism analysis is incomplete, and service life evaluation is inaccurate are solved, and support can be provided for reliability evaluation, structure optimization and service life prediction of the silicon-based optical interconnection chip.

The invention discloses an on-chip optical interconnection and switching chip and an application system thereof. Wherein the on-chip optical interconnection and exchange chip is integrated by a power divider, a bidirectional optical transceiver unit and an optical switch unit; the application system of the on-chip optical interconnection and switching chip comprises a multi-wavelength light source used for generating multi-wavelength optical carrier signals, a transceiving unit control and clock module used for bidirectional transceiving unit feedback / amplifier control and clock synchronization, and an optical switching control module used for switching an optical switching unit switching link. The chips and the modules are used for realizing optical interconnection and optical switching of the special electrical computing chip ASIC. According to the invention, bidirectional optical interconnection and exchange of special computing electric chips such as a CPU, a GPU, a DPU and the like can be realized by utilizing an on-chip optical interconnection and exchange technology, the interconnection rate is high, the exchange switching time is short, computing power cluster networking oriented to artificial intelligence application can be supported, and the application prospect is good.

The invention relates to a packaging structure and packaging method for an optical module and an optical chip, and the packaging structure comprises a receiving end assembly, a stepped metal heat sink, and a silicon-based optical interconnection assembly which is pasted on the stepped metal heat sink. The silicon-based optical interconnection assembly comprises a laser, a silicon light beam splitter, a lens group, a light transmission compensation gasket, a silicon light modulator and an optical fiber array; coplanar coupling is formed between the laser and the silicon light beam splitter. The silicon light beam splitter and at least part of the collimating lens in the lens group are fixed on the light transmission compensation gasket; the optical fiber array and the silicon light modulator realize waveguide matching in an active coupling mode; the silicon light modulator and the receiving end assembly are separately arranged at least at a preset interval, and the optical fiber array and / or the receiving end assembly are / is covered with a metal isolation cover. According to the invention, the problems of high cost of multiple light sources, easy pollution of an open light path and yield bottleneck caused by low-reliability glue in the prior art are solved, and finally, a packaging scheme which is compact in structure, stable in process and high in mass production is formed.

The present disclosure provides an integrated circuit (IC) structure. The IC structure includes an optical interposer having optical waveguides; a plurality of chip stacks disposed over the optical interposer, each of the plurality of chip stacks including a first photonic IC chip and a memory chip over the first photonic IC chip; and a plurality of first laser source chips disposed adjacent to the plurality of chip stacks, respectively, wherein the optical waveguides in the optical interposer are configured as an optical interconnect structure to couple with the memory chip through the first photonic IC chip.

The invention discloses a polarization insensitive filter based on a sub-wavelength grating structure, and belongs to the technical field of integrated photonic devices. The filter comprises an input transition waveguide, a multimode waveguide grating and an output transition waveguide which are connected in sequence. The multimode waveguide grating is composed of a central sub-wavelength grating waveguide and Bragg gratings symmetrically distributed on the two sides, and the effective refractive indexes of TE polarization and TM polarization are equal by adjusting the waveguide width and duty ratio of the central sub-wavelength grating, so that the polarization sensitivity of the device is eliminated fundamentally. And the input / output transition waveguide adopts a transition mode of mixing a tapered waveguide and a sub-wavelength grating waveguide, so that low-loss mode transmission between a straight waveguide and a multimode grating is realized. According to the invention, the anisotropic equivalent medium characteristic of the sub-wavelength grating is utilized, a function of simultaneously and effectively filtering TE and TM polarization is realized, and the filter has the advantages of polarization insensitivity, flexible design, compact structure, simple process and compatibility with a CMOS (Complementary Metal Oxide Semiconductor) process, and has important application value in the fields of optical communication, optical interconnection and the like.

The invention provides a high-density photoelectric common connection pinboard based on a low-loss silicon nitride grating coupler. The invention aims to overcome the difficulty that the existing photoelectric heterogeneous chip is difficult to integrate, stack and package, and realizes high-density interconnection between the chip and the interposer by using a grating coupling structure and a silicon through hole technology, thereby realizing high-integration low-loss packaging of the heterogeneous chip on the interposer. According to the invention, high-efficiency optical interconnection between the heterogeneous chip and the photoelectric co-connection intermediate layer is realized through the high-efficiency grating coupler, and high-density electrical interconnection between the chip and the photoelectric co-connection intermediate layer is realized through the TSV technology and the RDL technology. Meanwhile, the optical interconnection efficiency between the interposer and the chip is improved by utilizing the electrode patterning advantage of the RDL technology, and the self-alignment between the chip and the interposer is realized. The method has extremely high compatibility to the packaging scene of the existing photoelectric heterogeneous chip, so that the method has great significance in improving the integration density and reducing the interconnection loss of a photoelectric heterogeneous integrated system and promoting the practicability of the photoelectric heterogeneous integrated system.

According to the three-dimensional stacked photoelectric co-packaging structure and the packaging method thereof provided by the invention, the three-dimensional stacked structure is formed by bonding the optical chips with C2W of the adapter plate wafer, and the optical chips can be allowed to be processed separately and then bonded on the adapter plate wafer, so that the complexity of the packaging process is reduced, and the packaging reliability is improved; besides, a bonding pad of each layer of optical chip bonding pad region is in contact connection with a part of conductive via holes of the electric interconnection region, and an upper layer optical coupling region is arranged to shrink outwards relative to a lower layer optical coupling region to expose a first optical coupler in the lower layer optical coupling region, so that the areas of the optical chips are sequentially increased from bottom to top along the thickness stacking direction of the photoelectric switching structure; the electric interconnection structure is arranged on the outer side edge of the optical chip to form an inverted pyramid shape, the electric interconnection structure is distributed on the outer side edge of the optical chip, a conductive column structure can be effectively prevented from being manufactured on the optical chip, the process complexity is reduced, meanwhile, the optical interconnection structure is also distributed on the outer side edge of the optical chip, light in the optical chip can be directly coupled to a photoelectric transmission layer, and too high efficiency loss caused by too many optical coupling times is avoided.

The invention belongs to the field of photoelectric co-packaging, and particularly relates to a photoelectric co-packaging temperature control framework based on an embedded glass-based micro-channel. Independent lower-layer heat dissipation is carried out on a heat-sensitive component optical interconnection chip through an embedded glass-based micro-channel technology, an electric interconnection heat dissipation channel continues to use existing upper-layer heat dissipation, mutual isolation of two heat dissipation channels in the whole common packaging body is achieved, heat dissipation partition is achieved from a new dimension, and thermal crosstalk is avoided; the whole common packaging body dissipates heat at the upper layer and the lower layer, so that the effective heat dissipation area is greatly increased, and the heat dissipation capability of the packaging body is greatly improved; and the guidance quality of the heat dissipation channel is better through material selection and additional arrangement of the heat insulation layer. And a metal film temperature sensor can be additionally arranged, so that the temperature of a component can be monitored in real time, heat management regulation and control can be performed in a targeted manner, the temperature rise of a heating device and the heat contact efficiency between the micro-channels are balanced, and more efficient heat dissipation is realized.

The invention relates to the technical field of chip packaging, in particular to a photoelectric co-packaging underfill isolation packaging framework and process. According to the invention, the underfill glue blocking hole is additionally designed in the underfill glue diffusion area at the outer edge of the optical fiber slot hole on the adapter plate, and through the resistance effect (interface difference and liquid tension) of the underfill glue blocking hole on the flowing of the underfill glue, the glue overflow range is accurately controlled, and the underfill glue is prevented from covering the optical fiber coupler of the optical chip. By optimizing the underfill isolation design, efficient coupling of the optical chip and the optical fiber is ensured in the pollution direction of the underfill, meanwhile, the packaging gap between the photoelectric chips is reduced, and the packaging density and compactness are improved; the process tolerance, the product yield and the system performance of photoelectric packaging are remarkably improved, and the method is particularly suitable for the application fields of high-density and high-performance calculation and optical interconnection.

The invention provides a photoelectric chip common packaging piece, an optical communication module and a preparation method, the photoelectric chip common packaging piece comprises a carrier plate, an optical chip and an electric chip, one side of the carrier plate is provided with a mounting surface, the mounting surface is provided with an electric interconnection structure, the carrier plate is internally provided with a conductive through hole and an optical interconnection structure, and the conductive through hole is electrically connected with the electric interconnection structure; the optical chip and the electric chip are both arranged on the mounting surface of the carrier plate, the optical chip is electrically connected to the electric chip through an electric interconnection structure, one side, facing the mounting surface, of the optical chip comprises an optical device, and an optical signal emitted by the optical device penetrates through the carrier plate through the optical interconnection structure. Compared with the prior art, efficient conversion and transmission of optical signals and electric signals are achieved, the interconnection distance between chips is shortened to a large extent, signal transmission loss and delay are reduced, signal integrity is improved, and therefore reliable transmission of high-frequency signals is achieved.

The invention relates to the technical field of chip reliability testing, and discloses a silicon-based optical interconnection chip dynamic life test system and method.The system comprises a stress loading module, a state monitoring module and a self-adaptive control module, and the stress loading module receives actual working load change characteristics of a chip to be tested; generating and applying dynamic stress matched with an actual scene; the state monitoring module monitors the real-time state of the loaded chip, and collects and outputs multi-dimensional data of optical loss, heat distribution and material deformation; and the adaptive control module analyzes the data to judge the degradation degree of the chip, dynamically adjusts stress parameters, returns the stress parameters to the stress loading module to optimize loading, outputs a service life evaluation result, and outputs a test stopping signal and records failure service life data when the data exceeds a safety range. The method corresponds to the system. According to the application, real simulation, comprehensive monitoring and accurate evaluation of the life test are realized, the test authenticity and the life evaluation accuracy are improved, and support is provided for chip reliability verification.

The invention discloses an optical interconnection link assembly, an optical interconnection link training method and an acceleration cluster system, and relates to the technical field of optical interconnection, and the method comprises the steps: allowing an optical interconnection link to enter a training process when a switching assembly successfully receives a detection character sequence sent by an opposite side, so as to guarantee the normal communication of the optical interconnection link, the success rate and the reliability of link establishment are improved, only when the bidirectional communication link of the optical interconnection link is successfully established, the actual data transmission function can be performed through the optical interconnection link, the limitation of traditional copper cable interconnection is solved, an efficient and stable data transmission link based on PCIe optical interconnection is provided, and the data transmission efficiency is improved. And low-loss and long-distance transmission is realized.

The invention relates to a chip and a module for optical interconnection, and a device and a system using the optical interconnection module. The chip comprises photon integrated circuit sub-modules, each sub-module comprises a plurality of first optical switching units, and each first optical switching unit is configured to selectively output an optical signal input by a first optical input port of the first optical switching unit through any optical output port; an on-chip optical switch which is optically connected with the first optical switching unit and is configured to select an output port to output an optical signal input by any one optical input port of the on-chip optical switch; a plurality of modulators optically connected to the first optical switching unit; a plurality of detectors, at least a portion of which is optically connected to the on-chip optical switch; a plurality of first optical couplers configured to optically connect the first optical switching unit with a first external optical fiber array; and a second optical coupler in optical connection with at least a portion of the detector and configured to transmit the optical signal from the second external optical fiber array to the portion of the detector.

Provided is an interposer comprising: one or more photonic waveguide; one or more microwave circuit; one or more optical interconnect; and one or more electronic interconnect, further configured to support a quantum sensor, and methods of operating and fabricating thereof. Further provided is a the interposer containing one or more classical sensors. Further provided is a network of quantum sensors supported by said interposers.

The present invention discloses a microwave topological photonic crystal metasurface antenna, which belongs to the field of communication technology. The present invention adopts a layered structure similar to a patch antenna, including a ground plate, a dielectric layer, a topological photonic crystal, a rectangular metal frame, and a microstrip feeder arranged from bottom to top. The topological photonic crystal is arranged above the dielectric layer, the rectangular metal frame is coated on the periphery of the topological photonic crystal, and the microstrip feeder is connected to the rectangular metal frame. The present invention can achieve multi-band characteristics and extended bandwidth. In addition, most of the electromagnetic waves propagated by the antenna within the band gap range are suppressed, and only electromagnetic waves of the angular state frequency can propagate, with smaller return loss, and the topological angular state can achieve unidirectional radiation, with better directivity at high frequencies. As a result, the antenna performance is greatly improved, which is very suitable for on-chip optical interconnection and photonic chip integration, and meets the needs of 5G / 6G communications, quantum computing, etc. for miniaturized devices.

The invention discloses a test system and method for an optical engine module, an evaluation board, a storage medium and a product, and relates to the technical field of communication, and the system comprises the steps: carrying out the active test and passive test of a to-be-tested transmission link which is disposed between a switching assembly and a first connector and is adjustable in electrical interconnection parameter, covering an electrical-optical full link, and carrying out the passive test of the to-be-tested transmission link; active testing is carried out on a to-be-tested transmission link under current electrical interconnection parameters through the switching component to locate a performance critical value, passive performance parameters of a target to-be-tested transmission link under a critical state are measured through the testing component, a critical failure state is accurately associated with physical layer defects, design allowance is conveniently deduced in a reverse mode, and the performance of the to-be-tested transmission link is accurately determined. The interconnection design parameters of the optical engine module are determined based on the parameters, compatibility is improved, the problems of fuzzy performance boundary, unknown design margin and compatibility risk caused by lack of systematic testing in related technologies are solved, and the beneficial effect of providing quantifiable design basis for PCIe optical interconnection channels is achieved.

The application relates to a packaging structure and a packaging method of an optical module and an optical chip, wherein the packaging structure comprises a receiving end assembly, a stepped metal heat sink and a silicon-based optical interconnection assembly attached to the stepped metal heat sink; the silicon-based optical interconnection assembly comprises a laser, a silicon optical beam splitter, a lens group, a light-transmitting compensation gasket, a silicon optical modulator and a fiber array; the laser and the silicon optical beam splitter form a coplanar coupling; the silicon optical beam splitter and at least part of the collimating lenses in the lens group are fixed on the light-transmitting compensation gasket; the fiber array and the silicon optical modulator realize waveguide matching through an active coupling mode; the silicon optical modulator and the receiving end assembly are arranged at a distance of at least a preset interval, and the fiber array and / or the receiving end assembly are covered with a metal isolation cover. The application solves the yield bottleneck caused by high cost of multiple light sources, pollution of an open light path and low reliability of glue in the prior art, and finally forms a packaging scheme with compact structure, stable process and high productivity.

Technologies for bridge dies for optical interconnects are disclosed. In an illustrative embodiment, build-up layers are adjacent a substrate, and a bridge die and a photonic integrated circuit (PIC) die are each mounted on the substrate. An xPU die is mounted on the build-up layers and the bridge die, and another electronic integrated circuit (EIC) die is mounted on the bridge die and the PIC die. The bridge die can both transfer electronic signals between the XPU and the EIC die as well as provide power signals from the substrate through one or more through-silicon vias defined in the bridge die. The power signals can be provided to the PIC die, which allows for a shorter path for a power signal compared to passing the power signal through the build-up layers. The shorter path for the power signal can improve power delivery integrity and reduce parasitic power delivery drops.

The present invention relates to a computing system, comprising a plurality of computing devices. Each of the computing devices is configured with a plurality of computing modules and a plurality of optical interconnect expansion cards, and each of the optical interconnect expansion cards is provided with an on-chip optical switch and at least one first optical switching unit. The optical interconnect expansion cards of the plurality of computing devices communicate by means of optical fiber connections; moreover, by means of controlling the first optical switching units and / or the on-chip optical switches, a first part of the plurality of computing devices forms a first super node, with the topology of a communication link of the first super node comprising a two-dimensional torus topology. The two-dimensional torus topology may be configured to comprise first ring topologies, where the computing devices in the first part form a one-dimensional torus in a first direction; at least two first ring topologies are arranged in a second direction; and at least some of the computing devices in the at least two first ring topologies form second ring topologies with a one-dimensional torus in the second direction, where the second direction intersects the first direction.

The embodiment of the utility model relates to an optical emission module and an optical interconnection structure. The light emitting module comprises a first electric chip used for providing a driving signal; the laser is connected with the first electric chip and is used for emitting light under the action of the driving signal, and the light emitting direction of the laser deviates from the first electric chip; the light path adjusting unit is arranged on a light emitting path of the laser, and the light path adjusting unit is used for adjusting a light path of a light beam from the laser, so that a preset included angle is formed between emergent light and incident light of the light path adjusting unit.

The invention belongs to the technical field of optical fiber communication, and discloses an internal and external optical interconnection architecture of a chip. The chip internal and external optical interconnection framework comprises a printed circuit board, a glass substrate, a chip unit and an external optical interface. The glass substrate is arranged above the printed circuit board, the chip unit is arranged above the glass substrate, and the external optical interface is arranged on the side surface of the glass substrate; a rewiring layer and an optical waveguide are arranged in the glass substrate, and the rewiring layer is arranged below the chip unit; the chip unit comprises a main chip, a storage chip, an electronic integrated chip and a photonic integrated chip; the photonic integrated chip is optically coupled with an external optical interface through an optical waveguide. The invention further provides a manufacturing method of the chip internal and external optical interconnection architecture. The chip internal and external optical interconnection architecture is the chip internal and external optical interconnection architecture. According to the invention, the electrical interconnection distance of high-speed data transmission can be greatly shortened, the transmission rate and the signal quality are improved, and the device power consumption is reduced.

An electronic device may include a photonic integrated circuit (PIC) coupled with a substrate. The PIC may communicate a photonic signal with one or more optical fibers. The PIC may process the photonic signal into an electronic signal. The PIC may extend between a first end and a second end. An electronic integrated circuit (EIC) may be coupled with the substrate. The EIC may communicate with the PIC. The EIC may transmit the electronic signal to the PIC. The EIC may receive the electronic signal from the PIC. The electronic device may include a lens assembly. The lens assembly may be coupled with the first end of the PIC. In an example, optical interconnects of the PIC are aligned with the lens assembly such that the lens assembly is configured to transmit the photonic signal communicated between PIC and the optical fibers.

The invention discloses an on-chip fully-integrated optical circulator based on phase modulation. The on-chip fully-integrated optical circulator comprises a substrate, a buried oxide layer, an optical waveguide layer, an upper cladding and a metal layer used for manufacturing metal electrodes, the substrate, the buried oxide layer, the optical waveguide layer, the upper cladding and the metal layer are stacked, the optical waveguide layer comprises two input / output optical waveguide groups, a four-port resonant cavity and two metal electrode pairs, and the metal layer comprises four modulation areas; four ports of the resonant cavity are respectively connected with four interfaces of the modulation area, each input / output optical waveguide group is connected by a bent optical waveguide and coupled to the resonant cavity, the middle of the metal electrode pair is bent to form a coplanar waveguide electrode, and the middle of each two ends of the modulation area is connected by the coplanar waveguide electrode. The fully-integrated optical circulator is realized under the silicon-based substrate for the first time, is compatible with current mainstream optical integration platforms such as SOI, LNOI and LTOI, and can be widely applied to large-scale photonic integrated chips, such as the fields of optical communication, optical sensing, on-chip optical interconnection and the like.

The invention provides a Micro-LED-based optical interconnection chip and a packaging method, and relates to the field of chips, the Micro-LED-based optical interconnection chip comprises N optical modules, each optical module comprises an SoC chip, a light emitting unit and a light receiving unit, the light emitting unit and the light receiving unit are arranged on the SoC chip, and lenses are arranged on the light emitting unit and the light receiving unit respectively; the first substrate is provided with a through groove, each optical module is electrically connected with the first substrate, and the light emitting unit and the light receiving unit are located in the through groove; the back surface of the second substrate is provided with a waveguide structure, the waveguide structure comprises a plurality of waveguide blocks, the end part of each waveguide block is provided with a total internal reflection mirror TIR, and the light emitting unit on one SoC chip reflects light to the light receiving unit on another SoC chip adjacent to the SoC chip through the total internal reflection mirror TIR so as to realize signal transmission of the adjacent SoC chips. The Micro-LED array can become an ideal scheme for short-distance optical communication by virtue of the advantages of parallel architecture, ultra-low power consumption and high stability.

This disclosure provides an optical interconnect module, an optical interconnect device, and a computing system. The optical interconnect module includes a photonic integrated circuit chip and a transceiver chip. The photonic integrated circuit chip includes a first optical switching section and a second optical switching section. The first optical switching section includes a plurality of first optical switching input ports, a plurality of first optical switching output ports, a plurality of second optical switching output ports, and a plurality of third optical switching output ports. An optical signal input from each first optical switching input port is selectively output from a corresponding one of the plurality of first optical switching output ports, a corresponding one of the plurality of second optical switching output ports, or a corresponding one of the plurality of third optical switching output ports. The second optical switching section includes a plurality of second optical switching input ports and a plurality of fourth optical switching output ports, each of the plurality of second optical switching input ports being connected to a corresponding one of the plurality of first optical switching output ports.

Examples described herein relate to an interface coupled to a memory and circuitry, coupled to the interface. In some examples, the circuitry is to: based on a configuration, perform switching between packets sent by a first process to a second process by writing packets into a first region of memory and copying the packets from the first region of memory to a second region of memory. In some examples, the first region of memory is accessible to the first process via an optical interconnect and the second region of memory is accessible to the second process via a second optical interconnect.

The present invention relates to a computing system, comprising a plurality of computing devices. Each computing device is configured with a plurality of computing modules and a plurality of optical interconnect expansion cards, and each optical interconnect expansion card is provided with an on-chip optical switch and at least one first optical switching unit. The optical interconnect expansion cards of the plurality of computing devices communicate by means of optical fiber connections. At least one computing device among the plurality of computing devices serves as a backup device, and the remaining computing devices are working devices that operate normally. When one or more working devices among the plurality of working devices fail, the connection topology of the plurality of computing devices is reconstructed by controlling the first optical switching units and / or the on-chip optical switches on the optical interconnect expansion cards of the plurality of computing devices, so that the backup devices as many as the failed working devices become the working devices that operate normally.

The invention discloses an optical interconnection simulation method and system based on full-link parameter optimization, and the method comprises the steps: processing an original signal based on a coding module, a first feed-forward equalizer and a continuous-time linear equalizer, and obtaining a to-be-processed electric signal; modulating and converting the to-be-processed electric signal into a to-be-sent optical signal through a driving circuit, and sending the to-be-sent optical signal through an optical channel; sensing a to-be-sent optical signal through a photodiode to obtain a to-be-received electric signal, and processing the to-be-received electric signal through a trans-impedance amplifier to obtain a to-be-recovered electric signal; and processing the electric signal to be recovered through an automatic gain control continuous time linear equalizer, a decision feedback equalizer and a second feed-forward equalizer to obtain a target receiving signal corresponding to the original signal. The problem of collaborative optimization of electric-optical-electric link distortion compensation and noise suppression in the high-speed optical interconnection system is solved, and the simulation precision is improved to the transmission scene verification requirement of single wave 200Gbps (the data rate of transmitting 200gigabit bit per second) or above.

The embodiment of the invention provides a wafer-level chip packaging structure and electronic equipment, relates to the field of semiconductors, and aims to improve the transmission performance between chips. The wafer-level chip packaging structure comprises an adapter plate and a wafer-level chip. The adapter plate comprises a first rewiring layer and a second rewiring layer which are arranged in a stacked mode, the first rewiring layer comprises an optical interconnection channel, and the second rewiring layer comprises an electric interconnection channel. The wafer level chip is arranged on the adapter plate. The wafer level chip includes a plurality of device regions, each device region including at least one chip. Along a first direction parallel to the adapter plate, the chips in the two adjacent device regions are connected through an electric interconnection channel, and the chips in the two device regions at the two ends are connected through an optical interconnection channel. Along a second direction parallel to the adapter plate, the chips in the two adjacent device regions are connected through an electric interconnection channel, the chips in the two device regions at the two ends are connected through an optical interconnection channel, and the first direction and the second direction are crossed.