Data access method and device, hardware accelerator, computing equipment and storage medium

Abstract

The invention discloses a data access method and device, a hardware accelerator, computing equipment and a storage medium. The data access method comprises the following steps of: storing the ith input feature vector in the i%Bth cache block in the B cache blocks under the condition that input data is received and stored by taking a feature vector as a unit, at the moment, the storage address of the ith input feature vector being the next of the last storage address in the i%Bth cache block, wherein B and i are both natural numbers. Efficient data access in a convolutional neural network witha large convolution kernel size is realized. Therefore, hardware resources are saved, cost and power consumption are reduced, high calculation parallelism is supported, and system performance is improved.

Description

technical field [0001] The invention relates to a convolutional neural network, in particular to a data access technology of the convolutional neural network. Background technique [0002] Convolutional Neural Network (CNN for short) has achieved very good performance in fields such as image classification, detection, and video processing, and more and more scientific research is devoted to applying CNN to other fields. [0003] At present, CNN generally mainly includes convolutional layers, downsampling layers, and fully connected layers. By changing the number of layers and the connection method between layers, different network structures can be obtained, which are suitable for different application scenarios. [0004] Most CNN programs now mainly run on general-purpose processors CPUs, or use graphics processors GPUs to accelerate. Due to the relatively high power consumption and low energy efficiency ratio of CPU and GPU, some recent work proposes to implement CNN on F...

AI Technical Summary

Problems solved by technology

However, when the size of the convolution kernel is relatively large, for example, in the deep speech recognition system DeepSpeech2, the size of the convolution kernel is 41×21 in the first layer and 21×11 in the second layer. The existing CNN hardware implementation scheme (FPGA or ASIC, etc.) are difficult to support

Based on this situation, in order to obtain better performance, CNN hardware implementation requires higher data and task parallelism, and for the case of large convolution kernel size, data storage and scheduling (also referred to as "data" in this paper) Access") is especially a big challenge

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