FPGA graph processing acceleration method and system based on OpenCL

Abstract

The invention discloses an FPGA graph processing acceleration method and system based on OpenCL, and belongs to the field of big data processing. The method comprises the following steps: generating acomplete control data flow diagram CDFG according to an intermediate code IR obtained by disassembling; partitioning the complete CDFG graph again according to Load and Store instructions to obtain new CDFG instruction blocks, and determining a parallel mode between the CDFG instruction blocks; analyzing Load and Store instructions in all the new CDFG instruction blocks, and determining a division mode of the BRAM on the FPGA chip; and reorganizing an on-chip memory of the FPGA by adopting a BRAM division mode, translating all new CDFG instruction blocks into corresponding hardware description languages according to a parallel mode among the instruction blocks, compiling and generating a binary file capable of running on the FPGA, and burning the binary file to the FPGA for running. By adopting a pipeline technology and readjusting the instruction in the instruction block, the memory access frequency is reduced, and the memory access delay is reduced; on-chip storage partitioning is adopted, writing conflicts of different assembly lines on the same memory block are reduced, and therefore the system efficiency is improved.

Description

technical field [0001] The invention belongs to the technical field of big data processing, and more particularly relates to an OpenCL-based FPGA graph processing acceleration method and system. Background technique [0002] Graph is a classic data structure, which has the field of graph theory in theory, and in real life, many relationships can be abstracted into graphs. For example, power data analysis, social network, transaction network, transportation network and so on. People obtain the desired information by analyzing the characteristics of the network. For example, to obtain which characters are "Internet celebrities" in the design network, to obtain the optimal route between two places in the transportation network, and so on. Graph computing is to abstract the above-mentioned common practical problems into several classic problems, such as the SSSP algorithm to obtain the shortest distance between two points, and the PageRank algorithm to obtain the importance of...

AI Technical Summary

Problems solved by technology

However, this method has great disadvantages: (1) The above-mentioned decision-making strategy is a static method, and it is impossible to judge the scattered nodes generated in the dynamic process.

Compared with the above-mentioned heterogeneous execution mode, the communication overhead is removed, but it also brings many problems: (1) For tasks that are not very intensive in calculation or memory access, the advantages of FPGA's high parallelism are wasted

(2) FPGA on-chip cache is limited, how to achieve high performance under the premise of limited resources, which is very unfriendly to development users

The use of this type of development language has high requirements for development users; although the use of HLS language, a C-like language, to develop FPGAs reduces the difficulty of development users, but because the HLS language itself is not capable of expressing pipelines, it cannot give full play to the advantages of FPGAs; The use of OpenCL to develop FPGA not only maintains the characteristics of low difficulty in HLS language development, but also makes good use of the advantages of FPGA pipeline because OpenCL uses fine-grained pipeline mode for compilation in the compilation process.

However, due to common problems in graph computing: the Power-Law characteristics of graphs, communication between graph nodes, random memory access, etc., will lead to system performance degradation

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