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543 results about "Triacontagon" patented technology

In geometry, a triacontagon or 30-gon is a thirty-sided polygon. The sum of any triacontagon's interior angles is 5040 degrees.

Generation of three dimensional fractal subsurface structure by Voronoi Tessellation and computation of gravity response of such fractal structure

The invention is an entirely new application of domain characterization generated by Voronoi tessellation, which is very close to realistic geology and computation of gravity response of such domain, which has three dimensional fractal basin structure, and is favorable for oil exploration. In this work the interfaces or tessellating domains are represented by a set of parameters, which are referred as Voronoi centers. These parameters can be perturbed by any amount without getting into representational problems as faced by the conventional techniques. To accomplish such representation Voronoi tessellation is used, which in two dimensional space consists of enclosing every Voronoi center by a Voronoi polygon such that the common edge of adjacent polygons is perpendicular bisector to the line joining the Voronoi centers on both the sides of that edge. In this invention instead of using conventional Euclidian distances, the notion of Voronoi tessellation is generalized by using Ldistances, where p can hold any real value so that Voronoi domains are not necessarily polygonal. Desired fractal subsurface is generated using this approach that is quite close to the natural settings than the conventional planer or polygonal representation. Next, the gravity response due to this fractal subsurface structure has been computed. The new invention has a significant advantage over the conventional methods especially in geophysical inversion where initial model parameters are updated in each iteration, which can be done more easily and efficiently by Voronoi tessellation merely by changing Voronoi centers.
Owner:COUNCIL OF SCI & IND RES

Integrated circuit layout field domain identification and grid subdivision processing method and device

The embodiment of the invention discloses an integrated circuit layout field domain identification and grid subdivision processing method and device. The method comprises the following steps: vertically projecting a plurality of polygons of each layer of integrated circuit layout to the same layer to form a Delaunay triangular grid; combining the polygon information and the layer information of the edges of the polygons which are superposed after projection; aligning the grids to the edges of each polygon, calculating the intersection points of the edges of each polygon, adding the intersection points into polygon vertexes and grid nodes to form a first triangular grid, forming a set by the edges of the polygons by an edge exchange method, taking out the edges of the polygons, exchanging the edges of the polygons, and if the set is a null set, ending the exchange; superposing the layer information of the edges of the polygons into all triangles in the polygons; identifying and collecting triangles and polygonal edges contained in each parallel flat plate field domain according to the layer information of the triangles and polygonal edges; and carrying out grid subdivision processing on triangles in each parallel flat plate field domain. According to the invention, the accuracy and high efficiency of the field domain identification and grid subdivision processing method can be ensured.
Owner:北京智芯仿真科技有限公司

Metallic hollow columnar member

A metallic hollow columnar member with a polygonal cross-section having at least five vertices and sides extending between the vertices, is disclosed. The polygonal cross-section is divided by two vertices (A, B) with small inside angles into two perimeter segments with a perimeter comprising one or more sides, and at least one of the two perimeter segments contains at least four sides. The respective inside angles of at least three vertices (V(i)) included in the perimeter segment which includes the at least four sides are equal to or less than 180°, the distance (SS(i)) between each of the at least three vertices (V(i)) and a straight line (L) connecting the two vertices (A, B) is shorter than ½ of the distance between the two vertices (A, B), and the inside angle of the vertex (C) with the smallest inside angle among the at least three vertices (V(i)) is larger than the inside angles of the two vertices (A, B). Vertices (VI) are present on the perimeter segment including the at least four sides, respectively between the vertex (C) with the smallest inside angle among the at least three vertices (V(i)) and one (A) of the two vertices (A, B), and between the vertex (C) with the smallest inside angle and the other (B) of the two vertices (A, B), said vertices (VI) having inside angles larger than the inside angle of the vertex (C) with the smallest inside angle.
Owner:NIPPON STEEL CORP

Multi-layer integrated circuit layout polygon alignment and simplification processing method and device

The embodiment of the invention discloses a multi-layer integrated circuit layout polygon alignment and simplification processing method and device. The method comprises the following steps of projecting a plurality of polygons of a multilayer integrated circuit layout to a same layer, and forming a Delaunay triangular mesh according to a Delaunay triangulation algorithm; aligning the Delaunay triangular mesh to each edge of each polygon, calculating the intersection points of the edges of each polygon, and adding the intersection points into the polygon vertexes and the Delaunay triangular mesh nodes to form a first triangular mesh; on the basis, forming the inner and outer auxiliary polygons for clamping the polygons inside and outside each polygon, and controlling the distances betweenthe inner and outer auxiliary polygons and the polygons through the distance thresholds; and aligning and simplifying the edges of each layer of polygons falling between the inner and outer auxiliarypolygons. According to the present invention, the fragmentation problem after the multilayer polygons form the parallel flat plate field domain can be reduced, the unnecessary dense grids are reduced,the analysis and solving time and the required memory of the multilayer integrated circuit are shortened, the gaps among the polygons can be reserved, and the integrated circuit layout shape is basically not changed.
Owner:北京智芯仿真科技有限公司

A method for repairing defects and holes in three-dimensional mesh model based on characteristic lines

The invention discloses a method for repairing defects and holes of a three-dimensional mesh model based on characteristic lines, which comprises the following steps: 1) detecting characteristic lines: describing the corresponding principal direction curvature fitting extreme value on the mathematical definition of the characteristic lines on the surface of the three-dimensional mesh model which can represent the prominent geometrical characteristics; 2) matching of characteristic lines: selecting an optimal matching pair through a matching probability measurement standard for the characteristic lines detected in the step 1); 3) triangulation and thinning adjustment: after matching and bridging the characteristic lines, the original hole is partially changed into a plurality of polygonal sub-holes, and the basic surface is constructed; then Delaunay triangulation and edge scoring function are calculated for each polygon sub-hole, and an influence factor is assigned to each edge of thepolygon sub-hole to realize the anisotropic refinement of the mesh and the repair of the damaged area of the hole. The damaged area of the repaired holes can keep the same density with the surroundingtriangular mesh, and can be naturally connected with each other.
Owner:GUILIN UNIV OF ELECTRONIC TECH

Polygon adaptive simplification processing method and device for integrated circuit layout

The embodiment of the invention discloses a polygon adaptive simplification processing method and device for an integrated circuit layout. The method comprises the following steps of obtaining a plurality of polygons of the integrated circuit layout containing a plurality of vertexes, and forming a Delaunay triangular grid taking the vertexes of the polygons as the grid nodes; aligning the Delaunay triangular grid to each edge of the plurality of polygons according to an edge exchange method to form a first triangular grid; identifying all triangles in the plurality of polygons in the first triangular grid according to an extrapolation method, wherein the extrapolation method forms all polygons into a set; taking out the polygons from the set one by one, identifying the triangles, repeating the operation until the set is an empty set, and then ending the identification; and judging whether the edges of the plurality of polygons in the first triangular grid meet a preset rule, and performing the adaptive simplification processing on the plurality of polygons according to the quality of each triangle when the preset rule is met. According to the invention, the accuracy, completenessand high efficiency of the polygon adaptive simplification processing method for the integrated circuit layout can be ensured.
Owner:北京智芯仿真科技有限公司

Method for searching shortest path of inevitable node

The invention discloses a method for searching a shortest path of an inevitable node. The method comprises processing steps that S1, a Thiessen polygon is constructed; S2, if a starting point inevitable node and a terminal point inevitable node are not the same inevitable node, S3 is carried out; S3, adjacent Thiessen polygons are queried and combined to form a first combined polygon by taking theThiessen polygons where the starting point inevitable node is located as the starting point; S4, adjacent unprocessed Thiessen polygons are queried and combined to form a second combined polygon by taking the first combined polygon as a reference; S5, the isolated Thiessen polygons are combined into a certain combined polygon with adjacent common edges; S6, edges, which are not in the same combined polygon, of two vertexes in the Denaulay triangle are deleted; S7, if the condition that a node degree is greater than or equal to 3 does not exist in the remaining side lines in the combined polygon exists, S8 processing is carried out; and S8, side lines in each combined polygon are connected end to end, and the short connecting line is taken as a result. The method is advantaged in that processing difficulty, cost and time can be effectively reduced, and search efficiency is improved.
Owner:GUANGXI HUALAN GEOTECHNICAL ENG CO LTD

Two-dimensional rapid iteration method and device for electromagnetic response of three-dimensional large-scale integrated circuit

The invention provides a two-dimensional rapid iteration method for electromagnetic response of a three-dimensional large-scale integrated circuit. The two-dimensional rapid iteration method comprises the following steps: 1, dividing each layer of integrated circuit layout with a complex shape into polygons with simple shapes; 2, taking the influence of other layers as an additional source, and calculating the electromagnetic field and surface current distribution of each layer of the integrated circuit layout through a two-dimensional finite element method; 3, calculating the influence of the non-uniformly distributed surface current on the simple-shaped polygon on the field points through two-dimensional Gaussian integral based on a vector Green function of the influence of a point current source on the field points, and further calculating the influence of the non-uniformly distributed surface current on the complex-shaped integrated circuit layout on the electromagnetic field distribution of all other layers; and 4, judging whether the change quantity of the electromagnetic field distribution of all layers is smaller than a preset error threshold value or not, if yes, ending, and if not, turning to the step 2. The invention further provides a device of the method, and the electromagnetic response on the three-dimensional integrated circuit layout can be rapidly calculated through two-dimensional iteration.
Owner:北京智芯仿真科技有限公司
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