Integrated circuit layout field domain identification and grid subdivision processing method and device

An integrated circuit and grid subdivision technology, applied in image data processing, electrical digital data processing, image analysis, etc., can solve the problem that the accuracy, integrity and efficiency of the edge exchange method cannot be guaranteed and affect field recognition Accurate and efficient, easy to miss and other issues related to grid subdivision processing methods

Active Publication Date: 2020-01-14
北京智芯仿真科技有限公司
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Problems solved by technology

[0005] However, the inventor found in the process of implementing the present invention that in the prior art, in the process of field identification and mesh subdivision processing of the integrated circuit layout, the triangle mesh is aligned to each side of multiple polygons according to the edge exchange method In this

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  • Integrated circuit layout field domain identification and grid subdivision processing method and device
  • Integrated circuit layout field domain identification and grid subdivision processing method and device
  • Integrated circuit layout field domain identification and grid subdivision processing method and device

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Embodiment approach

[0138] As a possible implementation manner, the second processing module mainly includes:

[0139] The sorting and searching unit is used to sort all polygon vertices, and according to the sorting result, for each vertex that is not defined as a coincident vertex, search for a vertex of the polygon whose distance from the vertex is less than a predetermined threshold, and sort the vertex and the searched vertices are defined as a set of coincident vertices;

[0140] The coincident vertex processing unit is used for each group of coincident vertices, taking its center of gravity as a newly merged vertex, and replacing all the vertices in the group of coincident vertices with the newly merged vertices, and the associated edge of the newly merged vertices is The associated edges of all the vertices in the group of coincident vertices are merged, wherein the associated edges of the vertices of the polygon are polygonal edges whose endpoints are vertices of the polygon;

[0141] T...

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Abstract

The embodiment of the invention discloses an integrated circuit layout field domain identification and grid subdivision processing method and device. The method comprises the following steps: vertically projecting a plurality of polygons of each layer of integrated circuit layout to the same layer to form a Delaunay triangular grid; combining the polygon information and the layer information of the edges of the polygons which are superposed after projection; aligning the grids to the edges of each polygon, calculating the intersection points of the edges of each polygon, adding the intersection points into polygon vertexes and grid nodes to form a first triangular grid, forming a set by the edges of the polygons by an edge exchange method, taking out the edges of the polygons, exchanging the edges of the polygons, and if the set is a null set, ending the exchange; superposing the layer information of the edges of the polygons into all triangles in the polygons; identifying and collecting triangles and polygonal edges contained in each parallel flat plate field domain according to the layer information of the triangles and polygonal edges; and carrying out grid subdivision processing on triangles in each parallel flat plate field domain. According to the invention, the accuracy and high efficiency of the field domain identification and grid subdivision processing method can be ensured.

Description

technical field [0001] The invention relates to the field of integrated circuit layout field identification and grid subdivision processing, in particular to a method and device for integrated circuit layout field identification and grid subdivision processing. Background technique [0002] The layout of the integrated circuit is the intermediate link between the schematic diagram of the integrated circuit and the realization of the integrated circuit process, and it is an indispensable and important link. [0003] Since the thickness and layer spacing of the multilayer integrated circuit board are much smaller than the size of the board, the three-dimensional calculation field of the multilayer integrated circuit board can be simplified into multiple two-dimensional calculation fields, and the two-dimensional calculation field is the upper and lower layer The coupled parallel plate field is also the propagation area of ​​electromagnetic waves. The parallel plate field refe...

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Application Information

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IPC IPC(8): G06T7/62G06T7/11G06T7/13G06T7/155G06T7/187G06T3/00G06F30/392
CPCG06T3/0031G06T7/11G06T7/13G06T7/155G06T7/187G06T7/62
Inventor 唐章宏
Owner 北京智芯仿真科技有限公司
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