Multiport register file circuit

Abstract

The invention provides a multiport register file circuit comprising a write address decoder circuit, a read address decoder circuit, a first memory array, a second memory array, a first input data buffer circuit, a third input data buffer circuit, a first sense amplifier array, a third sense amplifier array, a second input data buffer circuit, a fourth input data buffer circuit, a second sense amplifier array and a fourth sense amplifier array, wherein the first memory array and the second memory array are respectively connected with the write address decoder circuit and the read address decoder circuit, the first input data buffer circuit and the third input data buffer circuit are mutually reversed and are connected with the first memory array, the first sense amplifier array and the third sense amplifier array are connected with the first memory array, the second input data buffer circuit and the fourth input data buffer circuit are mutually reversed and are connected with the second memory array, and the second sense amplifier array and the fourth sense amplifier array are connected with the second memory array. The multiport register file circuit can supply 17 read data ports and 9 write data ports at the same time, and each port has 32-bit data signals, thereby the multiport register file circuit is capable of being applied into a digital signal processor of a very long instruction word structure.

Description

technical field [0001] The invention relates to the technical field of digital signal processor design, in particular to a multi-port register file circuit for a digital signal processor with an ultra-long instruction word architecture. Background technique [0002] In recent years, in terms of digital signal processors, in order to pursue higher and faster computing performance, the ultra-long instruction word structure has been widely supported. At the same time, the use of the ultra-long instruction word structure has also simplified the control circuit structure of the processor. Design costs are reduced and power consumption is reduced. Although the ultra-long instruction word structure increases the single-cycle data throughput of the digital signal processor, it needs to increase the number of ports of the internal register file of the processor to meet the requirements, and the current number of ports of the internal register file of the processor cannot meet the dem...

AI Technical Summary

Problems solved by technology

Although the ultra-long instruction word structure increases the single-cycle data throughput of the digital signal processor, it needs to increase the number of ports of the internal register file of the processor to meet the requirements, and the current number of ports of the internal register file of the processor cannot meet the demand, so It has become a bottleneck in the development of processors and urgently needs to be improved

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