Method for decreasing data access delay in stream processor

Abstract

The invention relates to a method for reducing the data access delay in flow processor, wherein the invention improves the first memory layer of flow processor, combines scalar DRAM and flow DRAM into chip external share memory shared by scalar processor and flow processor; and uses new method to transmit data flow between chip external share DRAM and flow register document SRF; and uses synchronous mechanism to relate RAW; the scalar processor and flow processor directly send request to the bus when accessing chip external data, to obtain bus priority, and send the accessed address to DRAM controller; the DRAM controller accesses chip external DRAM to obtain the data of DRAM and feedback data to scalar processor or flow processor. The invention can avoid overflowing SRF caused by overlong flow, to avoid transferring data several times in memory space to reduce the data access delay.

Description

technical field [0001] The invention relates to a method for reducing data access delay in a stream processor, in particular to a method for reducing data access delay in a stream processor oriented to intensive calculation. Background technique [0002] The stream processor based on the stream architecture is a typical representative of a new generation of intensive computing-oriented high-performance microprocessors, which are specially oriented to stream applications. A stream is an uninterrupted, continuous, and moving data queue, and the length of the queue can be fixed or variable. Streaming applications are mainly divided into two categories: one is media applications; the other is scientific computing. Streaming applications have the following main characteristics: Computational intensity, compared with traditional desktop applications, streaming applications perform a large number of arithmetic operations on each data fetched from memory; parallelism, mainly data-l...

AI Technical Summary

Problems solved by technology

[0022] It can be seen that the multiple transfers of data in scalar DRAM, scalar processor, processor interface unit, SRF and streaming DRAM caused by this one memory access will greatly increase the data access delay

Therefore, the existing stream processor data access method is inefficient, and the overhead of the data transmission process is high, and a new method is needed to reduce the data access delay

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