Method for decreasing data access delay in stream processor

A technology of stream processor and data access, which is applied in various digital computer combinations and general-purpose stored program computers, etc. It can solve the problems of increasing data access delay, high overhead of data transmission process, low efficiency of stream processor data access method, etc. , to achieve the effect of reducing data access delay and reducing the number of memory accesses

Inactive Publication Date: 2006-12-27
NAT UNIV OF DEFENSE TECH
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Problems solved by technology

[0022] It can be seen that the multiple transfers of data in scalar DRAM, scalar processor, processor interface unit, SRF and streaming DRAM caused by this one memory access will greatly increase the data access delay
Therefore, the existing stream processor data access method is inefficient, and the overhead of the data transmission process is high, and a new method is needed to reduce the data access delay

Method used

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  • Method for decreasing data access delay in stream processor
  • Method for decreasing data access delay in stream processor
  • Method for decreasing data access delay in stream processor

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Embodiment Construction

[0052] figure 1 It is a structural diagram of a stream processor published by the Stanford University Imagine Processor Research Group on the http: / / cva.stanford.edu / imagine website. In the design of stream architecture, the storage space of scalar processor and stream processor is separated logically, and two independent off-chip DRAM memories are also used physically, namely scalar DRAM memory and stream DRAM memory. There is no data path and control path between memories. The scalar processor and stream processor also use their own storage controllers, data paths of off-chip DRAM, control paths and corresponding chip pins, and the clock system is also independent. The storage system belonging to the scalar processor is only connected to the scalar processor, and the storage system belonging to the stream processor is only connected to the stream processor. As the coprocessor of the scalar processor, the stream processor is interconnected with the scalar processor by using...

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Abstract

The invention relates to a method for reducing the data access delay in flow processor, wherein the invention improves the first memory layer of flow processor, combines scalar DRAM and flow DRAM into chip external share memory shared by scalar processor and flow processor; and uses new method to transmit data flow between chip external share DRAM and flow register document SRF; and uses synchronous mechanism to relate RAW; the scalar processor and flow processor directly send request to the bus when accessing chip external data, to obtain bus priority, and send the accessed address to DRAM controller; the DRAM controller accesses chip external DRAM to obtain the data of DRAM and feedback data to scalar processor or flow processor. The invention can avoid overflowing SRF caused by overlong flow, to avoid transferring data several times in memory space to reduce the data access delay.

Description

technical field [0001] The invention relates to a method for reducing data access delay in a stream processor, in particular to a method for reducing data access delay in a stream processor oriented to intensive calculation. Background technique [0002] The stream processor based on the stream architecture is a typical representative of a new generation of intensive computing-oriented high-performance microprocessors, which are specially oriented to stream applications. A stream is an uninterrupted, continuous, and moving data queue, and the length of the queue can be fixed or variable. Streaming applications are mainly divided into two categories: one is media applications; the other is scientific computing. Streaming applications have the following main characteristics: Computational intensity, compared with traditional desktop applications, streaming applications perform a large number of arithmetic operations on each data fetched from memory; parallelism, mainly data-l...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/76G06F15/16
Inventor 文梅伍楠张春元任巨何义荀长庆杨乾明管茂林
Owner NAT UNIV OF DEFENSE TECH
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