Internal memory copying accelerating method and device facing multi-core microprocessor

A core microprocessor, memory copy technology, applied in machine execution devices, electrical digital data processing, instruments, etc., can solve the problems of low performance, low performance, long startup time of DMA equipment, etc.

Active Publication Date: 2013-04-03
NAT UNIV OF DEFENSE TECH
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Problems solved by technology

However, this DMA-based memory copy technology still has certain shortcomings, such as (1) DMA devices often require a long startup time, (2) the kernel needs to be notified through an interrupt after the copy is completed, (3) the support of the operating system is required
[0006] No matter which of the above memory copy implementation methods, there is a problem of relatively low performance
In addition, these memory copy implementation methods are mainly aimed at memory copy operations in single-core microprocessors, and do not give an optimization method for memory copy operations in multi-core microprocessors
In short, with the contin

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  • Internal memory copying accelerating method and device facing multi-core microprocessor
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  • Internal memory copying accelerating method and device facing multi-core microprocessor

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Embodiment Construction

[0060] Such as figure 1 As shown, the implementation steps of the memory copy acceleration method for multi-core microprocessors in this embodiment are as follows:

[0061] 1) Add memory copy instructions in the microprocessor instruction set, memory copy instructions include ordinary memory copy instructions, MPI point-to-point send instructions, MPI point-to-point receive instructions, MPI group send instructions and MPI group receive instructions; in the microprocessor An MPI communication acceleration module for executing memory copy requests based on MPI communication is established outside the instruction execution pipeline;

[0062] 2) Convert the decoded memory copy instruction into a corresponding memory copy request. If the current memory copy request is a normal memory copy request, distribute it to the memory copy unit in the instruction execution pipeline and jump to step 3); otherwise, it will The memory copy request is distributed to the MPI communication accel...

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Abstract

The invention discloses an internal memory copying accelerating method and a device facing a multi-core microprocessor. The method comprises the following steps: an internal memory copying instruction and an MPI (Multi Point Interface) communication accelerating module are added in a microprocessor instruction in a concentration manner to identify internal memory copying request types which are obtained by decoding; general internal memory copying requests are issued to an internal memory copying unit; MPI group communication requests or MPI point-to-point communication requests are issued to the MPI communication accelerating module; the MPI communication accelerating module merges and executes associated internal memory copying requests to improve internal memory copying performance and execution efficiency; and the device comprises a decoding unit, the internal memory copying unit, associated detecting parts, and the MPI communication accelerating module for executing the internal memory copying requests which constitute MPI group communication or MPI point-to-point communication. The method and the device have the advantages of high efficiency of internal memory copying, good performance of multi-core optimization, low hardware design complexity, good compatibility, low power consumption and simplicity in hardware realization.

Description

technical field [0001] The invention relates to the field of multi-core microprocessors, in particular to a memory copy acceleration method and device for multi-core microprocessors. Background technique [0002] With the rapid development of computing technology, application programs have higher and higher requirements on the processing capability of microprocessors. People improve the performance of the processor core by increasing the main frequency of the processor, adopting technologies such as superscalar and multi-threading. However, the above-mentioned technologies have gradually been unable to meet the needs of the rapid development of processors. The continuous improvement of clock frequency means that the power consumption of processors has increased sharply and clock synchronization has become more and more difficult. Mainstream processors no longer blindly pursue high main frequency. Given that the parallelism of the application itself often has certain limita...

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Application Information

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IPC IPC(8): G06F9/38G06F15/167
Inventor 郭御风石伟张明窦强龚锐邓宇任巨马爱永罗莉王永文
Owner NAT UNIV OF DEFENSE TECH
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