22 results about "Full Rate" patented technology

The invention discloses a transmitter based on a high-speed low-power-consumption data serialization and driving circuit, and the transmitter comprises a low-speed serialization module which is used for serializing 32 paths of input parallel low-speed data into 4 paths under the control of a multi-phase clock signal; the FFE 4-tap generation module is used for performing delay operation on the four paths of data under the control of a clock signal to obtain four groups of tap data; and the high-speed 4: 1 MUX hybrid SST driving module is provided with 2N first slices, the N first slices comprise K slices of PRE taps, L slices of MAIN taps, J slices of POST1 taps and H slices of POST2 taps, and the driving module is used for generating full-rate differential data according to the four groups of tap data and switching signals provided externally and realizing impedance matching of an output end. According to the invention, the number of used triggers can be reduced, full-rate nodes in the circuit are eliminated, the power consumption is reduced, the complexity of simulating the FFE is relatively low, and different channel losses can be compensated.

A method of operating a memory device includes receiving, from a memory controller, an operation command that is synchronized with a clock signal, receiving a data clock signal having a full-rate frequency and a synchronization pattern provided by at least one of a plurality of data signals. The clock signal and the data clock signal are then synchronized using a synchronization operation based on the synchronization pattern. The data clock signal may be received after a first delay time passes from a time point at which the operation command is received. The first delay time is a delay time necessary to prepare the synchronization operation.

The invention provides an FRIS-assisted physical layer security communication method and system, the physical layer security communication system comprises a base station and an FRIS, the surface available area of the FRIS is divided into a plurality of sub-areas, each sub-area comprises a plurality of reflection units, all the reflection units in each sub-area form a sub-array, and each sub-array comprises a plurality of reflection units. Only one reflection unit in each subarray is selected and activated, and the activated reflection unit is used as an activation unit for reflecting a transmission signal of the base station to a legal user; the method comprises the steps that an optimization problem is solved, the optimization problem takes maximization of the safety rate of a legal user as an optimization target, constant modulus constraint, phase shift discrete constraint and activation unit position constraint are taken as constraint conditions, and an activation unit position and a passive beam forming variable are obtained. Compared with the traditional RIS, the FRIS-assisted physical layer security communication method and system can significantly improve the PLS performance of the system, thereby improving the security communication level of the system.

The application belongs to the technical field of communication, and particularly relates to a full-rate communication system, method, terminal and storage medium based on 5G, which comprises a control module, an acquisition module, a communication module and a power module for powering the whole system; the control module is connected to external equipment through the communication module; the communication module comprises a low-rate communication unit, a medium-rate communication unit and a high-rate communication unit; the system integrates the low-rate, medium-rate and high-rate communication units, can intelligently select the most suitable communication mode for data transmission according to the size and type of target data, the flexibility ensures that the terminal equipment can work at the optimal communication rate and power consumption in different use scenarios, and avoids the problem of shortened battery life caused by long-time use of high-power communication technology in the traditional scheme. Meanwhile, since the communication rate can be flexibly switched according to actual needs, the system also effectively reduces the flow cost of the SIM card.

The invention discloses a shore ship adaptive communication method, system and device based on reconfigurable intelligent surface assistance, and relates to the technical field of communication and deep reinforcement learning. The method comprises the following steps: determining a target equivalent channel, an eavesdropping equivalent channel and a diagonal phase shift matrix to be optimized according to a first RIS phased array and a second RIS phased array; determining a base station channel and a superposition channel according to the diagonal phase shift matrix to be optimized, the target equivalent channel and the eavesdropping equivalent channel; determining a total safety rate according to the to-be-optimized beam forming vector and transmission data of the second base station, the to-be-optimized artificial noise vector of the first base station, a base station channel and a superposition channel; constructing constraint conditions according to the maximum transmitting power of the first base station, the to-be-optimized beam forming vector, the to-be-optimized artificial noise vector and the to-be-optimized diagonal phase shift matrix; and based on a multi-strategy value network fusion algorithm, solving a target optimization result by taking the maximum total safety rate as a target and taking a constraint condition as a constraint.

The application discloses a kind of joint security and covert communication methods based on dynamic mode switching mechanism, which first executes scene task loading and parameter initialization, obtains the task parameter set and channel state information of current transmission period, obtains the reflection coefficient matrix of intelligent reflecting surface.Secondly, according to the channel state information and the reflection coefficient matrix, the candidate parameter set of security communication mode and covert communication mode is generated respectively, and the executable strategy set and the performance evaluation result of two modes are obtained.Finally, according to the performance evaluation result of security communication mode and the preset switching threshold, dynamic switching is carried out between security communication mode and covert communication mode, the system performance of safety rate calculation current period is obtained, and the task parameter of next transmission period is updated.The application solves the problem that security communication and covert communication are usually designed separately, and it is difficult to unify and coordinate control according to real-time channel state, exposure risk and transmission demand.

This invention provides an analog adaptive three-tap decision feedback equalizer circuit for high-speed SerDes, which splits the input signal into three paths, reducing the frequency. Compared to full-rate decision feedback equalizers, this invention reduces timing requirements and the design complexity of the corresponding phase-locked loop (PLL) providing the clock, making it applicable to higher data transmission rates. Furthermore, the analog adaptive loop allows for appropriate adjustment of the multiplier tap coefficients, more effectively eliminating inter-symbol interference. Compared to adaptive circuits in mixed-signal circuits that require counters and DACs, this invention has lower design complexity, better convergence, and meets the requirements of high-speed transmission.

The invention discloses a transmitting device based on a DSP-DAC framework and a high-speed serial communication system, and relates to the field of serial communication, in the device, a digital processing unit processes a signal to be transmitted based on multi-tap FIR feedforward equalization to obtain B paths of parallel A-bit data signals; the low-speed data processing module obtains C paths of parallel A-bit data signals; the differential-pulse generation module under the ith group of DAC slices receives C paths of parallel ith-bit data signals so as to obtain C paths of parallel pulse signals, the merging and serializing driving module performs merging and serializing according to the C paths of parallel pulse signals, driving corresponding to the ith group of slice weight is performed through an SST driving structure so as to output a serialized differential signal corresponding to the ith bit, and the serial differential signal corresponds to the ith bit. And a target serialized differential signal is obtained through superposition. According to the scheme, parallel-to-serial processing and output driving are combined to set the merging-serializing driving module, and a full-rate signal node is only limited at a final output stage, so that the front-end circuit design is simplified, and high speed and completeness of an output signal are ensured.

This invention discloses a high-efficiency odd-rate clock data recovery circuit. It uses switched capacitors to implement the phase detector, effectively reducing the phase detector's power consumption and area. Furthermore, its equivalent resistance and subsequent small-loop filter capacitor achieve a large loop bandwidth independent of PVT, effectively increasing the frequency acquisition range, eliminating the frequency discrimination loop, reducing lock-in time, suppressing the phase noise of the ring oscillator, and improving the jitter tolerance performance of the CDR loop. In addition, the retiming of random data employs an odd-rate demultiplexing structure, reducing the operating frequency of the N-stage ring oscillator, buffer, and retimer to 1 / N of the full-rate structure. This effectively reduces the power consumption and parasitic effects of the CDR circuit. The use of a frequency accumulator cleverly multiplies the odd-rate sub-rate clock by N to a full-rate clock without introducing excessive power consumption and area, where N is an odd number.

The utility model discloses multi-channel full-rate bit error rate test equipment, which comprises an MCU (Microprogrammed Control Unit) controller, a pseudo-random code pattern generator, a pseudo-random code pattern detector, a clock source circuit, a signal shaping circuit and a power supply circuit, the MCU controller, the clock source circuit and the signal shaping circuit are connected with the pseudo-random code pattern generator and the detector. And the MCU controller receives a user instruction to set test parameters, flexible adjustment can be performed according to different requirements, and the universality and applicability of the equipment are enhanced. The clock source circuit provides a time reference for signal processing, ensures accurate generation and synchronous detection of pseudo-random code patterns, and improves the statistical accuracy of bit error rates. The signal shaping circuit balances and filters input signals, compensates transmission distortion, improves signal quality, reduces misjudgment caused by distortion, and improves error rate calculation precision. The pseudo-random code pattern generator and the detector count the number of error codes and calculate the error rate, and provide key data for evaluating the transmission quality of a communication system.

The invention discloses a high-efficiency low-computing-power physical layer secure communication method and device based on an intelligent metasurface and a medium. The method comprises the steps that S1, channel matrixes h1 and H2 between a base station and an expected user and between the base station and an eavesdropper are input; s2, setting the number of iterations I, and initializing the number of iterations i = 0 and u (0); s3, randomly generating S alternative RIS phase shift matrixes according to the ui; s4, obtaining an equivalent channel matrix according to the channel matrix h1 and an alternative RIS phase shift matrix, and calculating a corresponding precoding matrix W; s5, calculating the maximum reachable safety rate of each alternative RIS phase shift matrix according to the equivalent channel matrix, the channel matrix H2 and the precoding matrix W; s6, arranging the alternative RIS phase shift matrixes theta in a descending order according to the maximum reachable safety rate; s7, selecting S'elite 'RIS phase shift matrixes theta with the maximum safety rate, S8, updating u (i + 1) based on the selected S' elite 'RIS phase shift matrixes theta, and S9, outputting a quasi-optimal RIS phase shift matrix theta for realizing high-efficiency low-computing-power physical layer safety communication.

A decision feedback equalizer providing pulse width adjustment, particularly comprising a pulse width adjustment circuit for receiving a plurality of amplified inputs obtained by corresponding different reference values, and adjusting the pulse width of the amplified inputs to conform to a 3-order adjustment signal according to a 3-order enable signal enabled by an initialization circuit, wherein a plurality of even-numbered channel signals are generated corresponding to a third-order even-numbered channel selection signal, a plurality of odd-numbered channel signals are generated corresponding to a third-order odd-numbered channel selection signal, even-numbered channel and odd-numbered channel half-rate sampling is carried out, first-order operation for reviewing the previous bit and second-order operation for reviewing the previous two bits are realized, and then full-rate output is obtained through combination.

The disclosed systems, structures, and methods relate to encoding and decoding information for transmission over a communication channel. The encoding method includes: distributing the information bits among m parallel polar codes such that each of the m parallel polar codes includes a subset of the information bits; dividing the subset of information bits in each of the m parallel polar codes into a guard information portion and a full-rate information portion; guarding the information bits within the guard information portion of each of the m parallel polar codes; setting multiple freeze bits in each of the m parallel polar codes; and generating a polar codeword for each of the m parallel polar codes.

The utility model discloses full-rate bit error rate testing equipment which comprises a clock source, an MCU (Microprogrammed Control Unit) control and a power supply circuit. Wherein the clock source circuit plays a key role, and a core chip U1 of the clock source circuit works cooperatively with a plurality of capacitors, resistors and diodes. A plurality of pins of the chip U1 are connected with a capacitor to be grounded, an internal circuit is stabilized, and a stable environment is created for clock signal generation. Accurate clock signals are obtained or output through pins connected with the clock generator, and a stable time reference is provided for error rate testing. The accurate clock signal enables the test equipment to be more accurate when detecting the change of the data transmission signal, effectively avoids the misjudgment caused by the inaccurate clock, remarkably improves the accuracy of the error rate test, and guarantees the reliability of the test result.

A single-particle reinforced half-rate decision feedback equalization circuit is based on a half-rate decision feedback equalizer circuit structure, and adopts an adder, a decision device, a three-stage multi-node upset resistant latch, an either-or data selector, a buffer and an adaptive controller. After entering the circuit, an input signal is divided into an odd path and an even path which are respectively balanced. A delay signal generated by the multi-node upset resistant latch unit acts with the tap coefficient and then is sent to the adder. Wherein the tap coefficient is determined by the adaptive controller circuit using an adaptive algorithm. Finally, the two paths of half-rate data are integrated into one path of full-rate data to be output. A half-rate structure is adopted, so that the problem that a traditional equalization circuit has strict requirements on a clock is solved. The multi-node upset resistant latch unit is added in the circuit, so that the influence of single event upset on intersymbol interference in a space environment is avoided. And the stability and accuracy of data storage are ensured.

The application discloses a near-far field robust security communication fusion method based on a non-orthogonal multiple access technology, and comprises the following steps: setting a channel model of a near field ISAC system, and acquiring a reachable rate of a user decoded by an eavesdropper; taking an error matched by a weighted beam pattern as an optimization target, setting an optimization problem P1 for the error matched by the weighted beam pattern; and adopting an S-Procedure technology and an alternating optimization technology to split the optimization problem P1 into sub-problems 1-3, and solving the optimization problem P1. The application sets a security rate of a user under eavesdropper interference, establishes a robust near field user model under the condition that an eavesdropping channel has a channel error, and under the influence of the error, guarantees that the near field user has a basic successful decoding rate and a minimum security rate requirement, and jointly optimizes a user service quality and a potential target sensing performance.

The invention discloses a method, device and terminal for enhancing transmission security by using channel reconfigurability, and the method comprises the steps: constructing a target communication system, and constructing a target signal model based on the target communication system, the target communication system comprises a target base station configured with a movable antenna, a target obstacle, a target user, a target eavesdropper and a virtual line-of-sight link established through a target RIS; a target constraint condition is obtained based on the target communication system, a target problem is constructed based on the target constraint condition, and the target problem is used for designing the maximum safety rate of the target communication system in combination with a beam forming matrix, a sensing signal, a phase shift matrix of the target RIS and the antenna position of the target base station; and solving the target problem to obtain the maximum security rate of the target communication system. According to the method, the problem solving difficulty is reduced while the channel freedom degree is fully mined, and the safety communication level of the user is further improved.

The invention provides a fractional feed-forward balanced transmitting circuit and a transmitter, in the fractional feed-forward balanced transmitting circuit, a line multiplexing module is used for outputting high-speed multiplexing data to a retimer; the retimer is used for delaying and outputting a time sequence high-speed signal to the feed-forward equalization module; the clock distribution circuit is used for outputting a delay control signal to the feed-forward equalization module; and the feed-forward equalization module is used for distributing the time sequence high-speed signal to a plurality of taps according to the control signal, performing fractional equalization on each tap according to the delay control signal, and synthesizing and outputting a full-rate data signal. According to the invention, the window time for acquiring the time sequence high-speed signal is distributed to each tap through the delay control signal output by the clock distribution circuit, so that each tap can freely slide back and forth, and fractional equalization is realized.

This invention discloses an IRS-assisted secure rate maximization design method under interruption probability constraints, belonging to the field of wireless communication technology. In a communication system model involving a transmitter, smart reflector, desired receiver, and eavesdropper, this invention introduces a probabilistic constraint to ensure the interruption probability of the secure transmission system remains within a tolerable range, proposing a secure rate maximization problem with this constraint: since phase shift, power allocation, and transmission rate are coupled in the objective function and the probabilistic constraint. This paper first utilizes the exponential distribution of received signal power to transform the difficult-to-handle probabilistic constraint into a deterministic constraint. Then, using the Alternating Optimization (AO) method to fix the beamforming matrix of the transmitter and the phase shift matrix of the smart reflector respectively, and through inequality transformations and solving the Rayleigh quotient problem, it effectively solves the problem of optimal phase shift, power allocation, and transmission rate design for secure transmission under uncertain channel conditions, where the probabilistic constraints of coupled variables are difficult to handle.

The application discloses a high-efficiency low-computing-power physical layer security communication method and device based on an intelligent metasurface and a medium, and comprises the following steps: S1, inputting a channel matrix h1 and H2 among a base station, a desired user and an eavesdropper; S2, setting an iteration number I, and initializing the iteration number i=0 and u (0) ; S3, randomly generating S candidate RIS phase shift matrices according to u i ; S4, obtaining an equivalent channel matrix according to the channel matrix h1 and the candidate RIS phase shift matrix, and calculating a corresponding precoding matrix W; S5, calculating a maximum achievable secure rate of each candidate RIS phase shift matrix according to the equivalent channel matrix, the channel matrix H2 and the precoding matrix W; S6, arranging the candidate RIS phase shift matrices Θ in descending order of the maximum achievable secure rate; S7, selecting S' "elite" RIS phase shift matrices Θ with the maximum secure rate; S8, updating u (i+1) based on the selected S' "elite" RIS phase shift matrices Θ; and S9, outputting a quasi-optimal RIS phase shift matrix Θ, so as to realize high-efficiency low-computing-power physical layer security communication.

The invention discloses a physical layer transmission method and related equipment, and belongs to the technical field of wireless communication. The method comprises the steps that a composite signal is sent to an unmanned aerial vehicle node, a cooperative node is indicated to interfere with an eavesdropping node through an interference signal, and the composite signal comprises a confidential information signal and an artificial noise signal which are subjected to sending power modulation according to a preset power distribution proportion; determining a safety outage probability according to the target safety rate, the signal to interference plus noise ratio of the received signal corresponding to the unmanned aerial vehicle node and the signal to interference plus noise ratio of the received signal corresponding to the eavesdropping node; taking the safety outage probability as a constraint condition, solving a first target function taking the target safety rate as an optimization target, and obtaining an adjustable power distribution proportion enabling the target safety rate to reach a maximum value; and carrying out sending power modulation on the confidential information signal and the artificial noise signal according to an adjustable power distribution proportion enabling the target safety rate to reach the maximum value.

A method for generating a clock signal includes: dividing an input clock signal to obtain a first in-phase output clock signal; frequency-dividing an inverted version of the input clock signal to obtain a first quadrature output clock signal; delaying an edge in the input clock signal to obtain a second quadrature output clock signal; selecting a full rate output in a first mode of operation to provide a multi-phase output clock; and selecting a half-rate output in a second mode of operation to provide a multi-phase output clock. The first quadrature output clock signal is a quadrature version of the first in-phase output clock signal. The first in-phase output clock signal and the first quadrature output clock signal are included in a full-rate output. The second quadrature output clock signal is included in the half-rate output and is a quadrature version of the input clock signal.