9 results about "Half Rate" patented technology

The present disclosure provides a low-distortion PAM-4 optical transmitter with a piecewise compensation scheme for VCSEL-based optical communication links. The input half-rate least significant bit (LSB) and most significant bit (MSB) data streams of the transmitter are firstly encoded into half-rate unary-weighted data streams by thermometer encoders. The half-rate unary-weighted data streams are then fed into three data slices with 2-tap feed-forward equalizer (FFE), continuous-time linear equalizer (CTLE), pre-emphasis circuit for serialization and piecewise pre-distortion. Finally, outputs from the three data slices are added in the form of current and fed into VCSEL. A thermal control loop is implemented to monitor the temperature of the VCSEL as well as provide compensation to the bias current of the VCSEL.

There is provided a system and a method for filtering out glitches in a SerDes transmitter. The SerDes transmitter includes a latency generation block, and a 2-to-1 serializer. The latency generation block is configured to synchronize a feed forward equalization (FFE) signal to a half rate domain by creating a latency in a FFE enable signal, and provide the synchronized FFE enable signal to a plurality of synchronized FFE selection multiplexers. The SerDes transmitter further includes a 2-to-1 serializer that is configured to filter out a glitch using the synchronized FFE enable signal in the half rate domain.

This application discloses an LVDS adaptive frame synchronization system, comprising: a transmitting end: a clock generation module providing multi-rate clocks; a data parallel-to-serial conversion module converting parallel data into a high-speed serial bit stream under clock control; a multi-functional auxiliary channel parallel-to-serial conversion module interleaving and encoding auxiliary control information and synchronization information into a composite bit stream; and an LVDS driver group converting signals into differential signals for transmission. The receiving end: an LVDS receiver group converts differential signals into single-ended signals, including multiple data signals, one auxiliary channel signal, and one half-rate clock signal. A serial-to-parallel conversion and synchronization control module uses a half-rate clock to perform DDR sampling of the data and auxiliary channel signals. Synchronization information is extracted by sampling on the falling edge of the auxiliary channel signal, and auxiliary control information is extracted by sampling on the rising edge. A synchronization detection unit obtains the capture sequence from the synchronization information, and a numerically controlled delay unit calculates the delay correction amount based on the mapping relationship between the capture sequence and the correction signal to delay the data, thereby achieving adaptive frame synchronization.

An NRZ / PAM-3 / PAM-4 multi-mode transmitter comprises eight identical data channels and two identical differential feedforward clock channels, the differential feedforward clock channels generate two differential clock signals according to a half-rate differential clock and output to a receiving end, the data channels perform serialization, equalization and DBI encoding processing on a plurality of pseudo-random binary sequences (PRBS) according to a mode control word and a clock signal output by the differential feedforward clock channels, and output the DBI encoded data to the receiving end; through power optimal receiving end termination, clock embedded DBI and multi-mode architecture technology, the ability of low power consumption, high energy efficiency and high bandwidth transmission can be realized.

A single-particle reinforced half-rate decision feedback equalization circuit is based on a half-rate decision feedback equalizer circuit structure, and adopts an adder, a decision device, a three-stage multi-node upset resistant latch, an either-or data selector, a buffer and an adaptive controller. After entering the circuit, an input signal is divided into an odd path and an even path which are respectively balanced. A delay signal generated by the multi-node upset resistant latch unit acts with the tap coefficient and then is sent to the adder. Wherein the tap coefficient is determined by the adaptive controller circuit using an adaptive algorithm. Finally, the two paths of half-rate data are integrated into one path of full-rate data to be output. A half-rate structure is adopted, so that the problem that a traditional equalization circuit has strict requirements on a clock is solved. The multi-node upset resistant latch unit is added in the circuit, so that the influence of single event upset on intersymbol interference in a space environment is avoided. And the stability and accuracy of data storage are ensured.

The application relates to the technical field of optical communication, and discloses a device and a method for data alignment based on half-rate over-sampling clock, which comprises a transmitting end, an analog front end and an over-sampling data clock recovery end; the transmitting end is used for receiving a plurality of low-speed parallel data signals and clock signals, and performing multiplexing conversion, voltage driving and electro-optical modulation to obtain a first optical signal and a second optical signal; the analog front end is used for performing photoelectric conversion and linear amplification on the first optical signal and the second optical signal to obtain recovered data signals and recovered clock signals; and the over-sampling data clock recovery end is used for performing six-phase clock generation, dense half-rate over-sampling and digital phase judgment on the recovered data signals and the recovered clock signals to obtain an optimal sampling clock and aligned recovered data. Through the combination of the half-rate over-sampling and the digital phase judgment mechanism, the adverse effects caused by transmission disturbance can be reduced, the clock sampling data capacity can be improved, and the overall operation stability of the optical communication link can be improved.

The invention belongs to the technical field of high-speed digital circuit design, and particularly relates to a high-transmission-efficiency high-speed serial-parallel conversion circuit based on a multi-phase clock and a conversion method.The conversion circuit comprises a double-channel parallel sampling sub-circuit, a high-speed serial-parallel conversion sub-circuit, a high-speed serial-parallel conversion sub-circuit and a high-speed serial-parallel conversion sub-circuit, n / 2 groups of sampling units are used for sampling double-path data under different phase clocks, and each group obtains 2-bit continuous data; and synchronously outputting N-bit parallel data at the uniform clock edge. The serial-to-parallel converter is suitable for serial-to-parallel conversion requirements of any even number of bit widths such as 8 bits, 10 bits, 12 bits and 16 bits, and has the advantages of being high in universality, easy to implement, high in transmission efficiency, low in power consumption and the like.

The application discloses a kind of half-rate phase detector circuit, it includes D flip-flop DFF1, D flip-flop DFF2, D flip-flop DFF3, D flip-flop DFF4, D flip-flop DFF5 and D flip-flop DFF6;D flip-flop DFF1, D flip-flop DFF2 and D flip-flop DFF3 are used to sample input data signal, D flip-flop DFF4 is used to synchronize the output of D flip-flop DFF1;D flip-flop DFF5 and D flip-flop DFF6 are used to sample the output of D flip-flop DFF2, D flip-flop DFF5 and D flip-flop DFF6 are triggered by D flip-flop DFF4 and D flip-flop DFF3 respectively.The application can work at higher data rate and help reduce the power consumption of clock circuit, while it is easier to achieve rules and compact when layout wiring.

The application relates to the technical field of integrated circuits and provides a continuous calibration and adaptation circuit and method for a high-speed comparator. By utilizing a half-rate structure of the comparator and a setting including an odd path and an even path, a plurality of odd path samplers and a plurality of even path samplers are used to finely adjust respective decision threshold voltage of each sampler; by utilizing a time division multiplexing mechanism of the samplers, the configuration under normal communication and the configuration under calibration of the offset voltage are distinguished to realize continuous calibration and adaptation of the offset voltage of the comparator while ensuring normal communication; and the adjustment of the respective decision threshold voltage of the plurality of odd path samplers is performed by using the output of the even path of the previous input data, so that the calibration effect is not affected by the change of the threshold voltage during the calibration process.