358results about How to "Improve layout efficiency" patented technology

A method of gridded glyph geometric objects (L3GO) integrated circuit (IC) design, wherein at least one inter-level connect in a L3GO circuit design is represented as a point matrix glyph (PMG) on a L3GO grid. Each PMG connects a pair of conductors on the next adjacent (above and below) layer and includes an array (one or two dimensional) of point glyphs contained within a cage. The point glyphs may have uniform size and may be on minimum pitch. Each PMG may also include a flange on the above and below layer. A default flange insures adequate coverage of cut shapes represented by the point glyphs.

The invention discloses a tunnel boring machine active source three-dimensional seismic advanced geology exploration device and method. The device comprises a tunnel boring machine cutterhead and a tunnel boring machine body connected with the cutterhead, wherein a main control room is arranged in the tunnel boring machine body; a controller and a multichannel seismic wave data collecting instrument are arranged in the main control room; seismic source systems are respectively arranged at the front ends of the tunnel boring machine cutterhead and the tunnel boring machine body; a data collecting system is arranged at the rear part of the working surface of the tunnel boring machine body according to certain space observation mode; the controller is respectively connected with the multichannel seismic wave data collecting instrument, the seismic wave systems and the data collecting system; the multichannel seismic wave data collecting instrument is connected with the data collecting system. The device has the benefits that rapid, flexible and automatic arrangement of a seismic wave and a detector system is realized, the maintenance time of the tunnel boring machine is sufficiently utilized, the work efficiency of geological advanced prediction is greatly improved, the normal construction is not disturbed, and time cost and economic cost are saved.

The objective of this invention is to provide a head substrate capable of integrating driver transistors while keeping the size small even at high nozzle density, and integrating a functional circuit such as a temperature sensor or energy adjustment circuit. To achieve this, an ink supply port, a heater array which is arrayed along the longitudinal direction of the ink supply port and includes a plurality of heaters, a transistor array which is arrayed along the arrayed direction of the heater array and includes a plurality of transistors for driving a plurality of heaters, and a logic circuit which drives the transistor array are arranged on a head substrate. The logic circuit is arranged between the heater array and the transistor array.

A solid-state image capturing apparatus includes: a pixel array unit including two-dimensionally arranged pixels each including a photoelectric conversion unit, a transfer transistor that transfers charges accumulated in the photoelectric conversion unit, and a charge discharging transistor that selectively discharges the charges accumulated in the photoelectric conversion unit; and a driving unit that performs driving for reading signals from each pixel of the pixel array unit, and drives the charge discharging transistor by using a signal for the driving.

The invention discloses a monitoring equipment layout method and device and belongs to the field of monitoring. The method comprises: establishing a two-dimensional coordinate system according to basic data input by a user, and receiving a region that needs to be monitored, which is divided by a user, through the two-dimensional coordinate system; converting two-dimensional coordinate data in the two-dimensional coordinate system into three-dimensional coordinate data; calculating a region covering range of the region that needs to be monitored, an actual scene and a horizontal coverage area of the region that needs to be monitored; screening at least one group of monitoring equipment meeting rules from a pre-set specialist rule base according to the region covering range of the region that needs to be monitored, the actual scene and the horizontal coverage area of the region that needs to be monitored; determining the conformity of each group of the monitoring equipment in the screened monitoring equipment group, and determining an optimal monitoring equipment group; and calculating an optimal monitoring layout scheme of the optimal monitoring equipment group. With the adoption of the monitoring equipment layout method and device, the optimal layout scheme can be rapidly, directly and accurately simulated, so that the excessive dependence on the technological level and experiences of constructors is avoided; and the quality of projects can be ensured and the layout efficiency can be improved. Moreover, the monitoring equipment can be sufficiently utilized and the cost is saved.

The purpose of this invention is to provide a head substrate capable of increasing layout efficiency. To achieve this purpose, an ink supply channel is arranged, and a plurality of printing element arrays are arranged on at least one side of the ink supply channel, and a plurality of driving element arrays are arranged adjacent to the plurality of printing element arrays. A plurality of power supply pads and a plurality of ground pads are arranged in areas between the plurality of driving element arrays.

The invention discloses an electronic conference plate system based on a ZigBee wireless technology network, which consists of an identity recognizer, a control server, a wireless positioning data transmission host and an electronic conference plate. The identity recognizer comprises a control chip, a periphery circuit, a recognition sensor, an electronic screen, a wireless data transmission module and the like; the electronic conference plate comprises a control chip, a periphery circuit, a front screen, a back screen, a wireless data transmission extension and the like. A participant is recognized by the identity recognizer at the entrance through an RFID (Radio Frequency Identification Device) card that worn by the participant, and the electronic screen displays the seat and prompts the participant to find the seat; meanwhile, the information is transmitted to the electronic conference plate of the corresponding seat in a wireless manner, and the name is displayed on the electronic conference plate. The invention has the advantages of automatically recognizing the identity of the participant, realizing automatic registration sign-in and wireless management, ensuring good anti-counterfeiting function, saving a great deal of labor and resources, and the like; moreover, the invention achieves real informatization and intellectualization of conference management and is widely applied to various conference rooms and large and medium-sized conferences of various levels and classes.

The invention relates to an analogue integrated circuit layout designing method capable of improving layout efficiency. The method includes the following steps: (1) generation of a full-chip physical layout draft: automatic generation of a layout of various modules in a schematic circuit diagram and automatic generation of the hierarchical full-chip physical layout draft by using of process database devices of circuit design according to the circuit top-level principle, (2) full-chip layout design: optimization and adjustment on the position of the layout of the various modules in the full-chip physical layout draft, determination of routes of data lines and routes of signal lines, and optimization and adjustment on positions of key devices in the layout of the various modules, and (3) design of the full-chip physical layout: completion of the final layout design of the various modules, completion of connection of the signal lines among the various modules, then completion of connection of the full-chip signal lines among the various modules, and acquisition of the full-chip physical layout. The analogue integrated circuit layout designing method can improve the layout efficiency and guarantee consistency of parasitic parameters of the devices in technology, circuit and layout design processes, simplifies design procedures, and achieves the purpose of improving circuit performance.

The embodiment of the invention discloses a view component layout method and system. In the embodiment, a mapping relation between identification of view components and layout strategies is set in a client side, the client side only needs to determine the layout strategy corresponding to the identification of the first view component according to the identification of the first view component in atarget area currently needing layout and according to the mapping relation between the identification of the view components and the layout strategies, and the determined layout strategy is the layout strategy of a layout area which the first view component belongs to. In this way, different layout logics (the layout strategies are instantiation of the layout logics) can be sequentially obtainedin all layout areas through multiple times of layout. By means of the method, the layout structure of the view components in a UI is flattened, and the efficiency of view layout executed by the clientside is improved.

The invention provides a multipurpose optimization method for distribution of facilities in a plant, which comprises the steps of: 1. dividing distribution areas of facilities in the plant into operation units and obtaining related original parameters; 2. obtaining logistic relation parameters and non-logistic relation parameters of the operation units according to the original parameters obtained from the step 1; 3. building a multipurpose facility distribution optimization model; and 4. solving the multipurpose optimization model by using an NSGA (non-dominated sorting genetic algorithm) II, thus obtaining a Pareto solution set as a facility distribution optimization scheme set. With the method, the technical problem that multipurpose optimization distribution is carried out on the facilities in a building of the plant is solved, and the use of the method has the advantages of high distribution efficiency, high operation vision degree, good optimization effect, low use cost and strong university.

The objective of this invention is to provide a head substrate capable of increasing the layout efficiency by arranging circuit elements in a free area of the head substrate on which ink supply channels are staggered. More specifically, the circuit elements connected to a plurality of element arrays are arranged on the free area.

The invention discloses a subject visualization method for a Chinese document set. The subject visualization method comprises the steps of classifying the document set according to subjects, dividing the time periods of the document set, calculating subject frequency, ranking the subjects, generating a subject flow graph, extracting keywords expressing the content of the subjects, calculating and ranking the weights of the keywords and generating a character cloud. The subject visualization method further comprises an ordering method based on the subject frequency and geometrical complementarity, a character cloud arrangement method and a method for generating the detailed character cloud. The subject visualization method has the advantages that the subject visualization on the Chinese document set is achieved; the subject flow graph generated through the ordering method based on the subject frequency and the geometrical complementarity is more attractive, flatter, high in space use ratio and more beneficial to character cloud arrangement; the character cloud arrangement method can effectively utilize space, and arrangement efficiency is greatly improved; the detailed character cloud is generated, and all the keyword content of the subjects can be shown.

A detection device includes a drive circuit of a physical quantity transducer, a synchronization signal output circuit, and a detection circuit that performs detection of a physical quantity signal based on a physical quantity. The synchronization signal output circuit includes a delay locked loop (DLL) circuit that includes: a delay control circuit that outputs a delay control signal and a delay circuit that includes a plurality of delay units in which a delay time is controlled by the delay control signal; an adjustment circuit that includes at least one delay unit in which a delay time is controlled by the delay control signal, and outputs a signal obtained by delaying an input signal based on the output signal from the drive circuit to the DLL circuit; and an output circuit that outputs the synchronization signal based on multi-phase clock signals from the DLL circuit.

The invention discloses a photovoltaic array arrangement method and a photovoltaic array arrangement scheme automatic generation system, and the method comprises the steps: S1, determining an obstacleshadow shielding region in a photovoltaic installation region, and enabling a region, except the obstacle shadow shielding region, in the photovoltaic installation region to serve as an actual installable region; S2, in the actual installable area, arranging photovoltaic arrays according to the azimuth angles of the photovoltaic assemblies, the inclination angles of the photovoltaic assemblies and the minimum intervals of the photovoltaic arrays, and obtaining a corresponding photovoltaic array arrangement scheme; S3, calculating annual irradiation received by the photovoltaic system based onthe photovoltaic array arrangement scheme; and S4, repeating the steps S2-S3, taking the maximum annual irradiation received by the photovoltaic system as a target, obtaining an optimal photovoltaicarray arrangement scheme, and completing photovoltaic array arrangement. According to the method, the arrangement of the photovoltaic arrays in the irregular installation area can be optimally designed, and meanwhile, the influence of barrier shadows is considered.

The invention is a circuit board layout method, comprising the steps of: providing a circuit diagram; establishing and storing electronic components and their attribute parameters in a database; drawing the attribute parameters the circuit diagram indicates from the database and inserting the attribute parameters of electronic components in the circuit diagram in the indication positions of the circuit diagram; when converting a circuit diagram into a circuit layout diagram, a designer obtains sizes, pin positions and connection relations of electronic components and other graphic data at the time of circuit layout design according to the attribute parameters of electronic components in the circuit diagram. And the invention benefits circuit layout design, raising layout efficiency and reducing artificial mistakes.

The invention relates to the technical field of construction of foundation facilities of urban track traffic, in particular to a method for automatically arranging trackside equipment, which is suitable for a CBTC (communication-based train control) system. The method for automatically arranging the trackside equipment comprises the following steps of S1, establishing a trackside equipment foundation configuration database containing all trackside equipment; S2, using the trackside equipment as nodes, and designing a trackside equipment topology structure; S3, combining the trackside equipment topology structure to establish a trackside equipment parameter configuration database; and S4, according to the line arrangement data, calling the relevant parameters from the trackside equipment parameter configuration database, and adding the trackside equipment in the trackside equipment foundation configuration database into engineering drawing software, so as to complete the automatic arrangement of the trackside equipment. The method has the advantages that the labor and the cost are greatly reduced, the artificial error is reduced, and the accuracy of the arrangement of the trackside equipment is ensured; and meanwhile, the arrangement efficiency of the trackside equipment is improved, and the favorable technical support is provided for the full-automation design of the CBTC system.

The invention discloses a gridding method for one-line diagram layout and optimization of a zone electric distribution system. The method comprises the following steps of: gridding a layout space, forming a grid lattice of a node layout solution space and a line corridor space of lines, and limiting the node layout solution space in the grid lattice of nodes; describing each grid state by adopting a relevant enumeration variable; performing node layout, establishing a node layout model, and adopting a shortest Manhattan distance of the nodes as a target function for node layout and optimization; performing mapping and initialization, determining the position of a transformer substation in grids according to relative geographic information by utilizing hierarchical branch attributes of a power distribution line, and arranging branch contact lines of a distribution network by selecting a hierarchical layout algorithm; introducing a self-adaptive crossover probability, and introducing different crossover probabilities for different fitness values; and avoiding overlapping and crossing situations of the lines. The gridding method disclosed by the invention effectively assists in node layout and optimization of a one-line diagram and arrangement of the lines in the zone electric distribution system.

The invention relates to a surface mounting method for a printed circuit board, wherein the printed circuit board is provided with a large device including a large device body and a soldering pin. The method comprises the following steps: (1) obtaining an empty board including a first face and a second face, the first face being provided with a large device mounting area including a bonding pad area and a blank area; (2) a first side printing: printing solder paste in the bonding pad area; (3) gluing and the first face mounting: putting an adhesive in the blank area to form an adhesive layer and then mounting the large device on the large device mounting area; (4) reflow soldering: subjecting the mounted large device to reflow soldering; (5) second face treatment: subjecting the second face to conventional printing, patch mounting and reflow soldering. The method solves the dropping of the large device in the first face, does not need to increase the size of the PCB, reduces the production cost, improves the PCB layout efficiency, and is simple and convenient for industrial application.

A Flash memory array comprises a plurality of Erase Sectors (Esecs) arranged in a plurality of Erase Sector Groups (ESGs), Physical Pages (slices), and Physical Sectors (PSecs), and there is a non-binary number of at least one of the Erase Sector Groups (ESGs), Physical Pages (slices), and Physical Sectors (PSecs). A user address is translated into a physical address using modular arithmetic to determine pointers (ysel, esg, psec) for specifying a given Erase Sector (ESec) within a given Erase Sector Group (ESG); a given Erase Sector Group (ESG) within a given Physical Sector (Psec); and a given Physical Sector (PSec) within the array.

The invention provides an image information sending method and device, and a waterfall flow layout method and device. The image information sending method comprises steps of receiving an image ID of a request image sent by a client; obtaining address information and height information of the request image according to the image ID; and returning the address information and the height information to the client, so that the client can generate a waterfall flow layout of the request image. The method enables the client to obtain the height of an image without loading the image, greatly improves the efficiency of waterfall flow layout, and enhances the display efficiency of a whole webpage.

A detection device includes a drive circuit of a physical quantity transducer, a synchronization signal output circuit, and a detection circuit that performs detection of a physical quantity signal based on a physical quantity. The synchronization signal output circuit includes a delay locked loop (DLL) circuit that includes: a delay control circuit that outputs a delay control signal and a delay circuit that includes a plurality of delay units in which a delay time is controlled by the delay control signal; an adjustment circuit that includes at least one delay unit in which a delay time is controlled by the delay control signal, and outputs a signal obtained by delaying an input signal based on the output signal from the drive circuit to the DLL circuit; and an output circuit that outputs the synchronization signal based on multi-phase clock signals from the DLL circuit.

An intake structure in a fuel cell powered vehicle including a fuel cell using air and hydrogen as fuels, a supercharger for compressing the outside air and outputting the compressed air, a humidifier for humidifying the air compressed by the supercharger, a bypass passage for connecting the supercharger and the fuel cell to each other, and a bypass valve for opening and closing the bypass passage. The bypass valve is disposed on the outside relative to a straight line T1 connecting between the supercharger and the humidifier, and is disposed in the vicinity of the supercharger and the humidifier. With this configuration supercooling of a humidifier can be prevented, while eliminating the need for a warming member for the humidifier. Further, the intake system members can be efficiently arranged in the vehicle, while suppressing the pressure loss in the intake system.

The invention provides a construction site virtual construction restoration method based on BIM + GIS, and the method comprises the steps of collecting the topographic data of a project site, and forming a database; processing the data in the database to generate a GIS model; extracting coordinates and elevation information of the three-dimensional oblique photography data and the three-dimensional forward photography data through a Global Mapper, so a forward photography map is synthesized; combining the construction site three-dimensional model and the forward photography model, and positioning coordinates, sizes and forms of objects needing to be protected on the construction site or needing to be restored after a project is completed to serve as model data backup; positioning coordinates, sizes and forms of objects needing to be protected on a construction site or needing to be restored after a project is completed, and providing data help for follow-up reinforcement, protection and restoration scheme making and work. By utilizing the characteristics of high precision, visualization, high efficiency and the like of the BIM + GIS technology, a construction total plane arrangement diagram is deeply designed, and a project construction site is assisted to realize green construction.

The invention discloses a parametric design method based on skeleton association for a ship equipment base. The method comprises the following steps: S1, creating a ship equipment model library; S2, creating a parametric base knowledge base; S3, base intelligent arrangement based on skeleton association: intelligently selecting and calling an adaptive base template in the parametric base knowledgebase according to equipment properties during instantiated arrangement of a base of ship equipment, and performing skeleton association on the ship equipment and the base according to skeleton association information between the equipment properties and base properties, so that the base can move automatically along with the movement of the ship equipment; and S4, base intelligent modification based on skeleton association: when the ship equipment is modified, performing base model reorganization by the base according to the skeleton association information between the equipment properties andthe base properties. Through adoption of the parametric design method, base rapid generation and automatic matching can be performed; the base instantiated arrangement efficiency is increased; and the base design quality is enhanced.

The invention discloses a network topology layout method. The method comprises the steps of: fragmenting and dividing the network into a plurality of block networks; respectively carrying out topological layout on the ring sub-network and the chain / tree sub-network in each block network, dividing levels based on service characteristics of network elements, determining position information of eachnetwork element of each level of the ring sub-network according to a force steering algorithm, and carrying out layer-by-layer layout to construct a network topology of the ring sub-network; and taking the root node of each chain / tree-shaped sub-network as an initial position, determining the positions of the nodes on the chain of the chain / tree-shaped sub-network based on a force steering algorithm, carrying out layer-by-layer layout, and constructing the network topology of each chain / tree-shaped sub-network. Correspondingly, the invention further discloses a network topology layout system.According to the invention, the stable network topology can be rapidly obtained.

A three-state content addressable memory (CAM) cell comprising a pair of static random access memory (SRAM) cells each including a pair of cross-connected inverters for storing data values, and a pair of inverters for An access device for accessing complementary pairs of bit lines. The CAM cell further includes a pair of comparison circuits, each for comparing said data value stored in said SRAM cell with a search data value provided on a corresponding search line. A CAM cell has an equal number of n-channel and p-channel devices. CAM cells use P-channel transistors as access transistors to SRAM cells to improve the layout efficiency of the cell array. This implementation ensures a balanced number of p-channel and n-channel devices per cell while still providing excellent functional characteristics.

In order to do away with the need for a power source switching operation, and to improve motor regeneration charge efficiency in a hybrid vehicle, a one-way clutch is provided between an internal combustion engine and an electric drive motor.