Performance improvement method of stacked DRAM cache

Abstract

The invention provides a performance improvement method of a stacked DRAM cache, and provides a row buffer manager to help to shorten the access delay of the stacked DRAM cache and accelerate data access, so that the performance is improved. The method comprises the following steps that S1, a row buffer manager is provided and comprises a row state table, the row state table comprises a pluralityof row state entries, and each row state entry comprises an activation bit, a label value sequence, a label value filling bit and a waiting request number so as to describe the state of memory row data; S2, the row buffer manager is connected with the data access request queue, andinformation of a row state table is updated by the row buffer manager according to the data access request arriving inthe data access request queue; S3, the row buffer manager is connected with the cache controller, and the row buffer manager receives a command from the cache controller and updates information of the line state table; and S4, the row buffer sends a control command to the stacked DRAM cache through the cache controller according to the information of the row state table.

Description

technical field [0001] The invention relates to a method for improving the performance of a stacked DRAM cache. Background technique [0002] The memory wall problem in the context of big data processing exacerbates the problem of data transfer between on-chip processors and off-chip memory. Integrated on-chip stacked DRAM (3D DRAM) memory is an effective way to meet this challenge, and its advantages lie in high bandwidth and low power consumption. Therefore, on-chip stacked DRAM is used as the last level of on-chip cache to temporarily store data from off-chip memory, reduce the amount of data transmission on and off the chip, significantly reduce data transmission delay, and effectively improve system performance. On the other hand, the organizational structure and interface design of on-chip stacked DRAM are not friendly to cache access, which hinders further improvement of system performance and affects its performance as the last level of cache. [0003] The on-chip ...

AI Technical Summary

Problems solved by technology

If the target memory line is not in the line buffer, a high-energy, high-latency line miss is caused; in addition, even if the target memory line is in the line buffer, a cache miss may occur, resulting in additional delay and energy consumption

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