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Instruction control method aimed at stream processor

A technology of instruction control and flow processor, applied in the field of microprocessor design, can solve problems such as inability to obtain performance and weak data correlation, and achieve the effects of high memory access bandwidth, hidden access delay, and high computing performance

Inactive Publication Date: 2009-02-11
NAT UNIV OF DEFENSE TECH
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AI Technical Summary

Problems solved by technology

For stream applications with high data parallelism and computation-intensiveness, the data correlation in stream applications is weak, and it is easy to separate computation from memory access, so the general-purpose instruction control method cannot obtain great high performance

Method used

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  • Instruction control method aimed at stream processor
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  • Instruction control method aimed at stream processor

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Embodiment Construction

[0028] The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

[0029] see Figure 4 As shown, the present invention is an instruction control method for a stream processor, which divides instruction control into a stream-level program and a core-level program. The stream-level program is responsible for data scheduling between the computing core and the off-chip memory, and the core-level program completes The operation of data, the specific steps are:

[0030] 1. Initialize the scalar data of the kernel-level program. The stream-level program initializes the scalar data required during the execution of the core-level program into the microcontroller register through the control word transmission instruction. When the core-level program is executed, it broadcasts from the microcontroller register to the computing group through the communication instruction. in the unit. If the kernel-level pro...

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Abstract

This invention discloses a instruction control method for streaming processor, which divides the instruction control into flow-level process and core-level process, the flow-level process is responsible for data scheduling between calculation core and off-chip memory, the core-level process completes data calculation, and the steps is: (1) initializing scalar data of the core-level procedure, (2) preparing vector data for the core-level procedure, (3) start executing the core-level procedure, (4) executing the procedure, (5) storing vector data generated by the procedure into the off-chip memory, (6) reading scalar result of the procedure.

Description

technical field [0001] The invention mainly relates to an instruction control method in the field of microprocessor design, in particular to an instruction control method for stream processors with computation-intensive and data parallelism. Background technique [0002] With the continuous expansion of the computer field, a typical application - stream application is becoming the main load of the microprocessor. The so-called stream is an uninterrupted, continuous, and moving data queue. This kind of stream application has the following characteristics: calculation-intensive, a large number of arithmetic operations are performed on each stream element fetched; parallelism, mainly based on data-level parallelism. The correlation of flow elements in the data flow is weak, and the operations on different flow elements are relatively independent, so there is a large amount of data parallelism and good delay hiding; locality, including data reuse locality and producer-consumer ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38
Inventor 张民选邢座程蒋江杨学军齐树波阳柳曾献君马驰远李勇陈海燕高军李晋文衣晓飞张明穆长富倪晓强唐遇星张承义
Owner NAT UNIV OF DEFENSE TECH
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