Self-holding analog core testing shell

Abstract

The invention discloses a self-holding analog core testing shell in the technical field of system on chip designs of electronic information technology, comprising an analog test input motivating pathway, a self-holding analog testing interface, a test controller, an output analog switch and an analog test response outputting pathway, wherein the analog test input motivating pathway is connected with the self-holding analog testing interface; the self-holding analog testing interface is connected with the test controller; the test controller is connected with the output analog switch; the output analog switch is connected with the analog test response outputting pathway; and the self-holding analog testing interface and the output analog switch are respectively connected with an analog core. By means of the self-holding analog core testing shell provided by the invention, the motivation applying and the response analyzing of the analog test of multiplexing of multiple ports of single DAC (Digital-Analog Converter) and ADC (Analog-Digital Converter) are realized.

Description

technical field [0001] The invention belongs to the technical field of system-on-chip design of electronic information technology, and in particular relates to a self-holding analog core test shell. Background technique [0002] The core integrated in the System On Chip (SoC for short) needs to be wrapped by a test wrapper (Test Wrapper), which is used to isolate the core to be tested and access the test port in the test state. Since each IP core in the SoC is deeply embedded in the chip, and the test nodes are very limited, most of the cores need to use the test shell design to realize the test access of the core itself and the system-level test integration. Therefore, the test enclosure design has a decisive impact on the SoC test area cost and test time cost. [0003] For digital-analog hybrid SoC, the dedicated digital-analog hybrid ATE (Automatic Test Equipment) equipment has a high-performance analog test module, and its test cost is much higher than that of digital A...

AI Technical Summary

Problems solved by technology

In this case, multiplexing a single DAC and ADC simply cannot realize multi-port analog test stimulus application and test response analysis

If a DAC or ADC is added to each test port, the area overhead of the system on chip is further increased

[0005] 2. From the perspective of system test integration, this Shared Wrapper structure can only realize serial simulation test, that is, at the same time, only one core core test can be realized by controlling the simulation multiplexer. When multiple simulation When the core core is designed with this test shell, it will cause the superposition of test time, which will become the bottleneck of the entire SoC test time and significantly increase the cost of test time

[0006] Aiming at the defects of the Shared Wrapper structure of commonly used analog multiplexers, it is necessary to propose a new type of test shell to solve the problem of virtual digital testing of analog cores

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