Source-synchronous data link for system-on-chip design

A system-level chip and data link technology, applied in the field of IC products, can solve problems such as performance changes and soft-core performance not being "solid-state"

Inactive Publication Date: 2010-11-10
NXP BV
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

One drawback of soft cores is that the performance of soft cores is not "solid state"; implementations in different processes can result in performance variations
[0008] However, IoS technology poses some challenges t

Method used

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  • Source-synchronous data link for system-on-chip design
  • Source-synchronous data link for system-on-chip design
  • Source-synchronous data link for system-on-chip design

Examples

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Embodiment Construction

[0019] In the following detailed description, for purposes of illustration and not limitation, example embodiments disclosing specific details are set forth in order to provide a more complete understanding of embodiments in accordance with the present teachings. However, it will be apparent to those skilled in the art having the benefit of this disclosure that other embodiments in accordance with the teachings of the invention than the specific details disclosed herein are within the scope of the appended claims. Moreover, descriptions of well-known devices and methods may be omitted so as not to obscure the description of the example embodiments. Such methods and devices are clearly within the scope of the teachings.

[0020] One type of communication link that does not require a globally synchronous clock is an asynchronous data link.

[0021] figure 2 An example embodiment of a device 200 with an asynchronous data link 255 is shown. figure 2 The flow of data between t...

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Abstract

A method of producing an integrated circuit (700) using a system-on-chip (SoC) architecture includes providing a first circuit (710) in a first island of synchronicity (IoS); and providing a source-synchronous data link (755/757, 765/767) between the first circuit (710) in the first IoS and a hard core (720) in a second IoS for communicating n-bit data elements between the first circuit (710) and the hard core (720). The source-synchronous data link (755/757, 765/767) includes a set of n data lines (755, 765) for transporting the n-bit data elements between the first circuit (710) and the hard core (720), and a source- synchronous clock line (757, 767) for transporting a source clock between the first circuit (710) and the hard core (720) for clocking the n-bit data elements. The hard core (720) does not include a bus interface adaptor for interfacing with the source-synchronous data link (755/757, 765/767).

Description

technical field [0001] The present invention relates to the field of system-on-chip (SoC) design and integrated circuits fabricated through SoC design, and more particularly, to SoC design methods for interfacing memory subsystems with hard cores using source synchronous data links and the IC products manufactured by this design method. Background technique [0002] System-on-Chip (SoC) design is a common and ubiquitous method of manufacturing integrated circuits. The use of pre-designed and pre-verified hardware blocks, also known as IP cores, in SoC design is an important part of the effort to design and implement complex systems. [0003] As known in the art, soft IP cores or "soft cores" are blocks of digital logic designed to be implemented typically in application specific integrated circuit (ASIC) or field programmable gate array (FPGA) chips. A soft core is typically provided using a register transfer level (RTL) hardware description language (HDL) that defines hig...

Claims

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Application Information

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IPC IPC(8): G06F13/42
CPCG06F13/385G06F13/4273
Inventor 卡洛斯·巴斯托让-威廉·范德韦尔特
Owner NXP BV
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