Parallel interchanging switching designing method

Abstract

The technical proposal comprises: the parallel interchange box consists of N input controllers, m Crossbar interchange boxes with low speed input buffer and N output controllers. Each input controller contains N virtual output queues and a load divider. The virtual output queue is cell buffer used to save input cell. The load divider is used for keeping load balance and determining the cell sent to Crossbar interchange box in each time slot, and is composed of a cell dividing request generator, a Crossbar state monitor, an input polling pointer generator and a cell dividing arbitration logic. Each output controller comprises mN virtual input queues and a cell integrator. The virtual output queue is a cell buffer. The cell arriving at the output controller firstly queues at the virtual output queue. The cell integrator rearranges the cells and is composed of cell rearrangement request generator, output polling pointer generator and cell rearrangement arbitration logic.

Description

technical field [0001] The invention relates to a design method of a switching switch in network switching equipment, in particular to a design method of a parallel switching switch based on an input buffer crossbar (Crossbar). Background technique [0002] Switching switch is the core component of network switching equipment, which is responsible for transmitting input cells to output ports. At present, the centralized input buffer crossbar switch is widely used. It contains a number of input ports and output ports, and the scheduler determines the connection relationship between the input and output ports, and switches cells from the input port to the output port. [0003] In order to meet application requirements, network switching devices are developing towards higher port rates and larger scales, which will greatly increase the difficulty of designing centralized switches. Firstly, the high-speed ports lead to shortening of the scheduler’s working cycle, and it is nec...

AI Technical Summary

Problems solved by technology

The focus of PPS research is to theoretically explore the possibility of parallel switching switches providing 100% throughput and delay guarantees. It has high requirements for low-speed switching modules and requires the use of output buffer switching switches. Due to the poor scalability of output buffer switching switches, High requirements on memory bandwidth, difficult to adapt to the rate requirements of high-speed networks

Therefore, the implementation of PPS is difficult and difficult for practical application

[0011] The input controller of ADSA and the low-speed switching switch adopt the request-confirmation working method, which not only increases the communication overhead, but also increases the difficulty of synchronization, and also requires the use of a dedicated low-speed switching switch

Secondly, ADSA may send multiple cells belonging to the same flow to the low-speed switch in one arbitration period. On the one hand, this increases the demand for the buffer bandwidth of the input port; Using timestamps and PIFO queues to reassemble packets, resulting in additional bandwidth overhead and increased implementation costs

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