104 results about "Clock synchronisation" patented technology

The application discloses a robot joint driving board external control method, system and related device, which is used for realizing the externalization of the driving board to optimize the heat dissipation and space layout of the robot joint, and ensuring the timing coordination of the signal interaction between the driving board and the joint side. The method comprises the following steps: the driving board runs based on a preset control period, and sends a synchronization signal to the acquisition board through a synchronization signal channel at the starting stage of each control period; the acquisition board performs a clock synchronization operation in response to receiving the synchronization signal, so as to calibrate the internal working timing of the acquisition board; the acquisition board collects joint sensor data after performing the clock synchronization operation, and sends the joint sensor data to the driving board through a data communication channel; and the driving board performs timing alignment processing on the joint sensor data based on the timing corresponding relationship between the sending time of the synchronization signal and the receiving time of the joint sensor data, and completes joint control calculation.

An approach to obtain low latency association of the audio clock in a smartphone with an incoming RF message is to use an interrupt driven routine, where the receipt of the RF message preamble generates an interrupt that reads the audio clock counter since the start of the audio session. In some embodiments such an approach may be implemented on the specialized processing cores found in smartphones that control RF communication, sensor or audio processing.

An audio synchronization control method, apparatus, system, chip, and medium are disclosed. The method includes: in an audio playback state where audio data frames sent by an audio host are received, acquiring sampled data, i.e., the clock jitter of the starting frame of the audio data frame; determining the total clock jitter in the current audio playback state for each sampled data of the starting frame; obtaining a corresponding predicted value for the sampled data of the next starting frame based on the sampled data and filter coefficients corresponding to the current adaptive filter; updating the filter coefficients based on the prediction error corresponding to the predicted value; and determining the clock jitter prediction correction amount of the phase-locked loop (PLL) based on the prediction error and the total clock jitter, and adjusting the PLL clock. Through the learning of the adaptive filter during operation, the clock jitter of the audio host at the next moment can be tracked and predicted in real time, and the clock of the audio device can be dynamically adjusted, resulting in high accuracy of clock synchronization after correction and effectively avoiding audio transmission asynchrony.

This invention relates to the field of signal interference identification technology, and discloses a distributed communication cabinet group collaborative control method and system based on the Internet of Things, including: automatically collecting and semantically mapping full-dimensional data; calculating node collaborative adaptability to complete heterogeneous node admission judgment; dividing a decentralized dynamic collaborative domain; electing domain coordination nodes and building a distributed collaborative infrastructure; calculating decentralized distributed clock synchronization and deviation within the domain; planning a unified collaborative timing window and completing full-link timing binding; combining node twins to complete cross-validation and anomaly identification of collaborative data; building a three-layer hierarchical decision architecture; screening feasible collaborative strategies through multi-objective rigid constraints; completing distributed command interlocking and priority control; calculating and pre-diagnosing node failure probability through node twins; planning fault pre-collaborative backup strategies and executing three-level gradient self-healing; and completing incremental iteration of the collaborative decision model and full lifecycle collaborative operation and maintenance through federated learning.

Embodiments of the present disclosure relate to an apparatus for clock synchronization, a related method and a medium. In an aspect, based on performing a first set of addition or subtraction operations on a first bit value, the apparatus obtains a quotient of the first bit value divided by a predetermined divisor, wherein the first bit value represents time in a first time unit. Based on the first bit value and performing a second set of addition or subtraction operations on the quotient, the apparatus obtains a remainder of the first bit value divided by the predetermined divisor. The apparatus obtains a second bit value representing time based on the quotient and the remainder, wherein the second bit value comprises a first part and a second part, the first part corresponding to the quotient and representing time in a second time unit, and the second part corresponding to the remainder and representing time in the first time unit. The apparatus for clock synchronization provided by embodiments of the present disclosure improves the maximum clock frequency in realizing the time format conversion function, and meets the requirement of reducing cost.

This application discloses a clock synchronization method, apparatus, board, and computer-readable storage medium, relating to the field of network time synchronization technology. The service card encapsulates a device sending timestamp in a first NTP request message sent by the main control card based on the first current service system time to obtain a second NTP request message, which is then sent to the NTP server. Based on the second current service system time, the service card encapsulates a device receiving timestamp in a second NTP response message sent by the NTP server to obtain a first NTP response message. The first NTP response message is then sent to the main control card, allowing the main control card to calculate the network clock deviation between itself and the NTP server based on the first NTP response message, and adjust the main control system time accordingly. This method avoids the problem of large errors between the device sending timestamp and the device receiving timestamp, thus ensuring that the network clock deviation calculated by the main control card will not have significant errors.

This application provides a surface logging system, a network clock synchronization method, and electronic equipment, belonging to the field of petroleum logging technology. The method includes: periodically broadcasting time synchronization protocol data packets based on a clock server; synchronizing the current operating time of the depth tension display panel and the current operating time in the logging data uploaded by the first type of logging instrument to the logging network as the system reference time, based on the depth tension display panel and the first type of logging instrument; periodically broadcasting time synchronization protocol data packets to the logging network using a time synchronization protocol; receiving the time synchronization protocol data packets based on a second type of logging instrument and synchronizing the current operating time in the logging data uploaded by the second type of logging instrument to the logging network as the system reference time; or synchronizing the current operating time of the second type of logging instrument with the operating time of the depth tension display panel based on the depth tension display panel. This application's solution can realize logging operations in all logging scenarios.

Provided are a method and a device for real-time clock synchronization, the method including: creating a configuration task, a synchronization packet task, a follow-up packet task, a delay request packet task, a delay response packet task, and a timestamp update task with the same priority and same time slice; running each task based on the time slice and in a round robin mode; generating a hardware interrupt by timing based on a clock synchronization interval; responding to a hardware interrupt of the timer hardware interrupt, identify a master port for the synchronization packet task, to record the master port with a synchronization identifier in a synchronization port table; detect a synchronization packet sending event and a delay request packet receiving event on the master port, and record synchronization packet timestamp information for updating the synchronization timestamp table and delay request packet timestamp information for updating the delay request timestamp table.

The application provides a resource coordination and time synchronization method and system for a large-scale computing power cluster, and relates to the technical field of computing power network architecture. First, the computing power nodes are registered and maintained by an authoritative DNS. After receiving a task, the system intelligently selects the optimal target computing power node and plans the data transmission path. To achieve precise coordination, the system dynamically creates a clock synchronization domain according to the task, elects a master clock and plans the optimal clock synchronization path. Finally, the system encapsulates and packages the optimal task data transmission path, the master clock timestamp and the optimal clock synchronization path identifier, and distributes them to the related nodes, thereby realizing efficient resource coordination and high-precision time synchronization. The method not only realizes the optimal matching of tasks and resources, guarantees the efficiency of data transmission, but also guarantees the accuracy and reliability of time synchronization from the physical link, and finally realizes efficient resource coordination and high-precision time synchronization in the computing power cluster.

This utility model discloses a signal hub board and a grid screen control system for a mesh screen. The signal hub board includes an input interface, multiple output interfaces, and a signal distribution circuit. The input interface receives a drive signal from a receiving card, which includes a master clock signal and multiple parallel data signals. The signal distribution circuit includes a clock buffer module and a data buffer module. The clock buffer module receives the master clock signal and, through buffering and copying, generates multiple output clock signals that are the same number as the number of output interfaces and synchronized with the phase. The data buffer module buffers the multiple parallel data signals one-to-one to generate multiple output data signals. Each output clock signal is paired with its corresponding output data signal and sent to a single mesh screen module through the corresponding output interface. The signal hub board and control system of this application improve signal quality by centrally synchronizing and shaping the drive signals, thereby ensuring that the mesh screen can achieve smooth, clear, and high-quality video playback.

This invention discloses a switching module for a high-reliability clock synchronization system. The invention includes: a signal processing module comprising a receiving unit and a processing unit; the input of the processing unit is connected to the output of the receiving unit, used for level conversion of the time signal received by the receiving unit and determining the next hop transmission path of the time signal; a PTP clock module, the input of which is connected to one output of the processing unit, used for receiving the level-converted time signal; and a switching chip, one input of which is communicatively connected to the output of the PTP clock module via a PHY chip, and the other input of which is connected to another output of the processing unit, used for PTP clock synchronization based on the level-converted time signal. Compared with existing technologies, this invention significantly reduces the risk of single-point failure and adapts to heterogeneous network environments.

This invention discloses a control method and system for a distributed motion controller, relating to the field of motor control technology. The method includes: acquiring operational data from the motion controllers of each production line via real-time Ethernet and processing the acquired data; performing fuzzy inference based on the underlying single-axis servo fuzzy controller of the motion controller to obtain position feedforward compensation time and distributed clock phase adjustment; performing fuzzy inference based on the upper-level production line collaborative fuzzy scheduler of the main controller to obtain speed multipliers and global command timestamp offsets; generating motor control commands conforming to the real-time Ethernet protocol; and using a distributed clock synchronization mechanism to synchronously adjust the operating parameters of the servo motors of each production line. By real-time monitoring and scheduling of the motion controllers of multiple production lines, multiple production lines can cooperate with each other, achieving intelligent dynamic adjustment of the production line system, thereby improving the processing efficiency of the production line system.

Provided are a wireless communication method and a communication device. The method comprises: a first device sends a first signal to a second device, the first signal corresponding to a plurality of transmission occasions, or a plurality of signal segments of the first signal corresponding to one transmission occasion. The first signal comprises one of the following: a preamble; a transmission preamble; first indication information that indicates the start of transmission; and first information for acquiring clock synchronization. In one aspect, in the embodiments of the present application, a first signal may correspond to a plurality of transmission occasions, and correspondingly, if a second device detects a first signal sent on a certain transmission occasion among the plurality of transmission occasions, same can be understood as the second device detecting the first signal, which helps to improve the probability of the second device detecting the first signal. In another aspect, a plurality of signal segments of the first signal correspond to one transmission occasion, and correspondingly, if the second device detects a certain signal segment among the plurality of signal segments, same can be understood as the second device detecting the first signal, which helps to improve the probability of the second device detecting the first signal.

An apparatus for the high-bandwidth memory is disclosed. The Apparatus comprises; a plurality of high-bandwidth memory dies; a plurality of TSVs (Through-Silicon Via) each corresponding one-to-one with the high-bandwidth memory dies; a memory control module connected to the plurality of TSVs; a test module configured to detect defects in the high-bandwidth memory dies and TSVs; and a non-volatile memory configured to store defect location information of at least one faulty high-bandwidth memory die and at least one faulty TSV detected by the test module. The memory control module is configured to set the TSVs based on the fault location information stored in the non-volatile memory, thereby minimizing the complexity of path configuration even in cases where faulty high-bandwidth memory dies and their corresponding TSVs exist, enabling efficient handling of clustered faults, and maintaining the performance of clock synchronization.

This invention discloses a PLC-based collaborative control system for composite material molding production lines, belonging to the field of automated composite material molding technology. It includes a production line execution unit and a PLC collaborative control unit. The production line execution unit includes a front-end production line, which interfaces with shared equipment via a transfer module. The master station arbitration PLC, production line slave PLCs, and shared equipment are connected via a communication unit. The PLC collaborative control unit incorporates an automatic mold switching control module and a native PLC-based full-process motion learning unit. The master station arbitration PLC also performs global scheduling, global clock synchronization, global IO address mapping planning, mold switching, and motion learning. The production line slave PLCs communicate with each production line individually. This PLC-based collaborative control system for composite material molding production lines can achieve motion learning, automated mold switching, and dynamic collaborative control throughout the entire process from raw materials to finished products, adaptively matching the dynamic characteristics of the production line.

This invention discloses a fault-tolerant control method for explosion-proof industrial robots with multi-level safety redundancy, belonging to the technical field of explosion-proof industrial robot control. It includes constructing a nested double-layer physical protection structure and a parallel gas supply architecture with dual gas source redundancy; processing multi-source sensor data using a clock synchronization mechanism; predicting the trends of pressure gradients and Taylor series; adaptive calibration of initialization and dynamic leakage benchmarks; performing multi-dimensional risk assessment of the positive pressure cavity and classifying the explosion-proof industrial robot into four operating states; and executing graded active fault-tolerant control. By constructing a dual-gas source architecture and a double-layer protection system, this invention utilizes a control algorithm based on pressure gradient prediction to perceive and assess the robot's operating state, and executes strategies such as leakage compensation, backup gas source release cutoff, or emergency shutdown based on the assessment results, significantly improving the safety, reliability, and operational continuity of explosion-proof industrial robots in hazardous environments.

The application belongs to the field of electronic information technology, and discloses a kind of synchronization and parallel distributed positioning system and method of sensing, related equipment;Among them, the system includes a master device and several slave devices, each master device and each slave device includes wireless clock synchronization module, double loop structure clock jitter eliminator and wireless transceiver module connection, the master device and slave device in a positioning cycle, parallel execution clock synchronization process based on wireless clock synchronization module and signal acquisition process of wireless transceiver module;The application can significantly improve the positioning refresh rate and system real-time performance, and reduce the TDOA estimation error caused by phase noise to improve positioning accuracy.

This utility model discloses a multi-system, multi-channel digital TR synchronization circuit, comprising a GPS / BD timing module, a system clock source, a multi-channel digital TR board, and a system lead generation device. The rubidium clock and second pulse of the GPS / BD timing module are respectively connected to the system clock source and the lead generation device. The sampling clock and lead clock of the system clock source, and the lead signal of the system lead generation device are respectively connected to each multi-channel digital TR board. The system lead clock of the system clock source is also connected to the lead generation device. This scheme uses the rubidium clock and second pulse of the GPS / BD timing module as a reference, and the accuracy of the lead clock determines the synchronization accuracy (e.g., a 20MHz lead clock synchronization error ≤50ns). Multi-system expansion can be achieved by adding timing modules without refactoring the hardware architecture. Its hardware and software integration reduces FPGA logic complexity, reduces hardware costs by relying on chip synchronization functions and equal-length wiring design, and ensures multi-channel synchronization stability through same-source clock allocation and equal-length signal design.

An FRC module comprises an integrated RF / FPGA-based qubit control system that integrates analog bandwidth DACs / ADCs with a System on Chip including processors and a large FPGA. RF channels can be controlled by a single module with a high channel density and the channels can be re-programmed into any feedback configuration. The embodiments support FPGA- level optimal filtering, state discrimination and feedback for qubit control; and a clock-synchronized state machine for time-critical quantum algorithms such as gate optimization.

This invention relates to a vehicle-to-infrastructure (V2I) clock synchronization method, system, electronic device, and computer storage medium, belonging to the field of communication synchronization technology. The V2I clock synchronization method includes: acquiring Global Navigation Satellite System (GNSS) signals based on an onboard communication unit and a roadside communication unit respectively; determining vehicle-end time synchronization and roadside time synchronization based on the GNSS signals; compensating for the vehicle-end time synchronization based on the crystal oscillator frequency offset of the onboard communication unit to obtain compensated vehicle-end time synchronization; compensating for the roadside time synchronization based on the crystal oscillator frequency offset of the roadside communication unit to obtain compensated roadside time synchronization; and calibrating the compensated vehicle-end time synchronization and the compensated roadside time synchronization according to a preset period based on GNSS clock calibration pulses to obtain calibrated vehicle-end time synchronization and calibrated roadside time synchronization. This invention can guarantee the accuracy of V2I clock synchronization.

This invention belongs to the field of motor synchronous control, and particularly relates to a multi-motor global clock synchronization system and method based on a phase-locked loop (PLL). The system includes a clock generation module and N motor control channels. The clock generation module generates a global reference clock signal in a preset frequency band. Each channel includes a phase detection module, a trigger phase adjustment module, a PID calculation module, and a drive module. During operation, the phase detection module detects the phase difference between the trigger feedback signal of its channel and the global reference clock signal and outputs the deviation. The trigger phase adjustment module adjusts the phase of the trigger signal according to the deviation. When the phase difference is less than a preset locking threshold, it outputs a calibration trigger signal locked to the reference edge of the global reference clock signal. The PID calculation module is triggered only when the locking edge arrives to perform proportional-integral-derivative (PI) calculations and generate motor control quantities. The drive module drives the motor accordingly, thereby eliminating synchronization errors caused by phase mismatch at the trigger edge.

This invention relates to the field of wireless audio transmission technology, and discloses a method, device, and system for transmitting dual-source wireless audio. The method is applied to an audio device and includes: establishing a first communication link and a second communication link with a first audio source device and a second audio source device, respectively, to transmit a first audio stream and a second audio stream. The audio device serves as a peripheral device for the first communication link and a central device for the second communication link. When audio data transmission on the first and second communication links coexists, the link clocks of the first and second communication links are the same or synchronized, and the first and second communication links use time-division multiplexing and share time slots. This invention, by configuring the clocks of the two links to be synchronized and employing time-division multiplexing and shared time slots for coexistence, avoids the problem of time slot overlap and insufficient bandwidth when audio source devices simultaneously transmit and receive wireless audio, thus making fuller use of bandwidth resources.

Methods and systems are described for calculating lane-to-lane skew parameters from detected alignment symbols during a skew measurement mode of operation, detecting a command to switch from skew measurement mode to a transparent mode of operation, wherein each of the plurality of encoded data streams are routed to respective low-latency CDC FIFOs configured to store the encoded data streams using respective write clocks and to output encoded data streams based on corresponding read clocks, each read clock synchronized to a corresponding write clock, and adjusting a timing of a first encoded data stream relative to a second encoded data stream based on the set of lane-to-lane skew parameters generated in the PCS to reduce lane-to-lane skew.

The application discloses a battery energy storage system monitoring method based on Internet of Things, and relates to the field of energy management.The method establishes multiple source collection points on each Internet of Things monitoring node of the battery energy storage system, and under the synchronous sampling instruction of a master control module, real-time operation data is collected, and the collaborative collection of multi-node and multi-dimensional data is realized.The edge computing unit utilizes a CRC-32 cyclic redundancy check algorithm and a clock synchronization mechanism to automatically complete data integrity verification and timestamp alignment, thereby ensuring the synchronization and consistency of data uploaded by different nodes in the time dimension.Meanwhile, through the joint noise reduction mechanism of Kalman filtering and sliding median filtering, and the unit dimension standardization processing of a dynamic interval normalization algorithm, the data deviation caused by sensor jitter, communication interference and physical quantity difference is effectively eliminated, so that the node-level monitoring matrix has stable data structure and high-quality input when formed.

Devices, systems, methods, and processes that facilitate clock synchronization between access networks connected through a core network are described herein. Typically, clock synchronization over a core network is prone to jitters and wander. Therefore, the present disclosure provides clock synchronization using edge devices for stateless clock propagation from one access network to another via a core network. The core network acts as a transparent node where latency is calculated by a difference between transmit and receive timestamps of a timing packet. An ingress edge device may capture, in the timing packet, the receive timestamp of receiving the timing packet and forward the timing packet to an egress edge device. The egress edge device may update a correction field of the timing packet based on a difference between the receive timestamp at the ingress edge device and a transmit timestamp at the egress edge device and forward the timing packet.