548 results about "Clock synchronisation" patented technology

The present technology pertains to systems and methods for one-way authentication of quantum channels. A transmitter generates an entangled quantum state comprising a first state and a second state, modulates the second state according to a clock-synchronized pattern, and transmits it through a quantum channel to a receiver. The first state is retained and measured at the transmitter to extract quantum-state information. Authentication is performed based on this information, without requiring feedback from the receiver. The quantum-state information may be derived using quadrature measurements, Gaussian tomography, or other statistical analyses to detect whether the second state underwent irreversible interactions such as eavesdropping or decoherence. The system enables secure unidirectional quantum authentication, reduces protocol complexity, and supports real-time anomaly detection. It is compatible with continuous-variable quantum states, quantum key distribution (QKD), and scalable communication architectures.

The invention discloses a mold injection molding full-process automation system based on layered cooperative control, which comprises a central control layer, a module scheduling layer and an equipment execution layer, and clock synchronization among the layers is realized through an industrial Ethernet. The central control layer comprises a dynamic scheduling server and a digital twinborn verification module, the module scheduling layer comprises a mold intelligent scheduling module, an injection molding process control module and a product quality closed loop module, and the equipment execution layer comprises a manipulator cooperation unit and a sprue material processing unit. By constructing a three-layer cooperative control architecture of a central control layer, a module scheduling layer and an equipment execution layer and combining a modular hardware carrier and a cross-layer data closed loop, common industrial problems such as cooperative level splitting, mold control marginalization and abnormal response delay are systematically solved; and finally, the comprehensive benefits that the die changing efficiency is remarkably improved, the product reject ratio is greatly reduced, and the energy consumption is obviously reduced are achieved.

The invention discloses a current and voltage signal synchronous correction and output method and system, and relates to the technical field of power system analysis and control. Compared with a previous current and voltage signal correction method, the method solves the problems that traditional multi-channel signal acquisition depends on conventional clock control, and synchronization precision is insufficient; a conventional sampling circuit is weak in anti-interference capability. The problem that an existing scheme lacks efficient error prediction and dynamic optimization capability is solved. Through a multi-channel FPGA clock synchronization and double-differential sampling technology, complete acquisition of high-frequency transient characteristics of voltage and current signals is ensured; a dynamic calibration algorithm and multi-stage composite filtering are combined, so that common-mode interference and non-linear errors are effectively suppressed; and finally, through optical fiber isolation output and intelligent feedback control, signal full-link synchronous correction is realized, the electric energy metering error can be reduced, the fault positioning precision is improved, the characteristics of high precision, strong anti-interference and low energy consumption are realized, and a reliable data reference is provided for intelligent power grid and new energy grid connection.

The invention relates to the technical field of data processing, and discloses a mine production-oriented multi-source data acquisition and edge calculation fusion device, which comprises a clock synchronization access module, a data governance control module, a flow pipeline backpressure module, an AI reasoning optimization module, a rule closed-loop control module, a message safety uplink module and a center training iteration module, according to the method, the problem of difficulty in data fusion of multi-source equipment is solved, and the consistency of heterogeneous data in time and semantic dimensions is ensured; the stability of an edge computing system under a complex working condition is improved, and data loss and processing delay are avoided; collaborative decision-making of the AI model and the rule engine is realized, and the risk of false report and missing report is reduced; the security and reliability of the data transmission process are ensured, and local autonomy when the network is abnormal is supported; a model automatic iteration mechanism is established, and the ability of the system to adapt to different working conditions is improved.

The invention discloses a video time synchronization processing method and system based on a high-precision network timing protocol. According to the method, time frequency traceability is provided for an internal taming clock module and a clock synchronization module of a processing host through second pulse signals; the internal taming clock module selects to execute a clock taming operation or switch to a self-travel time mode according to whether the external time reference exists or not; according to the time synchronization detection result of the video synchronization processing module, if it is judged that the time synchronization difference between different cameras exceeds a preset range, hardware trigger signals are sent to the cameras through an external trigger generation module, so that camera parameters are adjusted, and key frames are generated; and the video synchronous processing module identifies key frames generated by the multiple cameras by adopting an image definition evaluation method, and completes time axis alignment of the video streams of the multiple cameras based on the key frames. According to the invention, the problem of low synchronization precision or accumulative error and network jitter in the prior art is solved; the time delay after the software is aligned is high, and the camera and the processing host lack feedback linkage.

The invention discloses an on-chip optical interconnection and switching chip and an application system thereof. Wherein the on-chip optical interconnection and exchange chip is integrated by a power divider, a bidirectional optical transceiver unit and an optical switch unit; the application system of the on-chip optical interconnection and switching chip comprises a multi-wavelength light source used for generating multi-wavelength optical carrier signals, a transceiving unit control and clock module used for bidirectional transceiving unit feedback / amplifier control and clock synchronization, and an optical switching control module used for switching an optical switching unit switching link. The chips and the modules are used for realizing optical interconnection and optical switching of the special electrical computing chip ASIC. According to the invention, bidirectional optical interconnection and exchange of special computing electric chips such as a CPU, a GPU, a DPU and the like can be realized by utilizing an on-chip optical interconnection and exchange technology, the interconnection rate is high, the exchange switching time is short, computing power cluster networking oriented to artificial intelligence application can be supported, and the application prospect is good.

The invention belongs to the technical field of data center network and clock synchronization, and discloses a dynamic time synchronization path optimization method and system based on topology awareness. The invention provides a closed-loop framework of state awareness-path optimization-resource assurance-dynamic adjustment and optimization: in the first stage, network topology, link load and PTP message performance data are periodically acquired through an SDN controller, and a global state view is constructed; in the second stage, the optimal path is dynamically calculated for the PTP synchronous flow through a multi-constraint optimization algorithm with the purpose of minimizing transmission delay jitter, and deterministic transmission is achieved in combination with bandwidth reservation and a priority queue; and meanwhile, a seamless switching mechanism of building first and disassembling second is introduced to adapt to the network state change in real time. On the basis of multiplexing existing hardware, the time synchronization error is remarkably reduced, the transmission stability and the dynamic adaptability are improved, microsecond-level time synchronization can be efficiently achieved, and the method is suitable for high-precision service scenes.

The invention discloses a multi-protocol compatible hydropower station field bus photoelectric signal synchronous acquisition device and method, and relates to the technical field of industrial bus testing, the device comprises a core control layer, a signal conditioning layer, a photoelectric interface layer, a clock synchronization layer, a power management layer and a data storage and transmission layer; the core control layer adopts a dual-core framework of a domestic Loongson 2K0300 main control unit and a domestic FPGA (Field Programmable Gate Array) time sequence control unit; the clock synchronization layer adopts a two-stage synchronization mechanism of'local crystal oscillator time sequence control + NTP network clock calibration '; and the signal conditioning layer is integrated with a multi-protocol self-adaptive conditioning module and an industrial-grade anti-interference module. The method comprises the steps of clock initialization and calibration, parameter configuration, photoelectric signal parallel acquisition and time sequence synchronization, and data preprocessing and transmission, so that synchronous acquisition of six types of bus protocol photoelectric signals is realized. The system has the advantages of multi-protocol compatibility, autonomous controllability, good portability and the like, and provides reliable data support for bus communication quality evaluation and fault diagnosis.

This application provides a clock synchronization method and a control system for a control system. The control system includes a first controller and a second controller. The first controller includes a first clock unit and a second clock unit, and the second controller includes a third clock unit. The clock of the first clock unit is different from the clock of the third clock unit, and the clock of the second clock unit is the same as the clock of the third clock unit. The method includes: the first controller and the second controller adding a timestamp to sensor data using a first clock, wherein the first clock is either the clock of the first clock unit or the clock of the third clock unit, ensuring clock consistency of the sensor data, thereby improving the accuracy of subsequent business processing.

Clock synchronization in a multichip module is provided. Relative clock skews among a plurality of digital devices are detected based on a pairwise exchange of clock signals between digital devices. In some aspects, the plurality of digital devices comprising at least one noncommunicating pair of digital devices. Based on the relative clock skews of the various devices, the respective clock signals of the plurality of digital devices are deskewed.

The invention discloses a voiceprint feature extraction and positioning method for a pipeline leakage point, and the method specifically comprises the following steps: S1, a voiceprint feature extraction stage: collecting a pipeline sound signal through a distributed sensor, extracting and optimizing a multi-domain voiceprint feature after adaptive denoising, and relates to the technical field of pipeline leakage detection. According to the voiceprint feature extraction and positioning method for the pipeline leakage points, multiple leakage point signals of the same pipeline section can be effectively separated and positioned by improving a FastICA algorithm and a density peak value clustering algorithm, the positioning error can be controlled within 0.8 m, the positioning precision in a multi-leakage point scene is remarkably improved, and the positioning accuracy is improved. Based on an edge node-cooperative gateway-cloud center information physical system architecture, a distributed clock synchronization protocol is adopted, cooperative monitoring and simultaneous positioning of multiple branch pipelines are achieved, the response time is shortened to be within 3 seconds, and the problems of positioning conflict and response delay of the multiple branch pipelines in a traditional method are solved.

The invention relates to the technical field of wireless communication, in particular to a low-frequency special data link communication system fusing a central networking and an ad hoc network. According to the technical scheme, the system comprises a central networking communication module, an ad hoc network communication module, a special data link module, a low-frequency communication optimization module, a clock synchronization module and a fault self-healing module. Through dynamic cooperation of the central networking and the ad hoc network, low-frequency signal special optimization, industry customization of a special data link and multi-module cooperation of precise clock synchronization and efficient fault self-healing, the problems of incomplete communication coverage, easy transmission interruption, poor industry adaptability and high information security risk in a complex environment are solved; the system is large in communication coverage range, stable in operation and accurately adaptive to different industry scenes, meanwhile, the real-time performance and safety of data transmission are guaranteed, the scene requirements of emergency rescue, industrial control monitoring, remote area communication guarantee and the like are met, and the stability and reliability of communication are effectively improved.

The invention discloses a secure clock synchronization method, a storage medium and electronic equipment. The secure clock synchronization method comprises the following steps: acquiring running states of a first clock channel and a second clock channel; acquiring a phase difference between the first clock channel and the second clock channel; adjusting the phase difference between the first clock channel and the second clock channel; and monitoring the operation states of the first clock channel and the second clock channel. According to the full-clock synchronization method, the storage medium and the electronic equipment, the clock signals of the first clock channel and the second clock channel are synchronized, it is ensured that the two clock channels can output high-precision synchronous clock signals, the SIL4-level safety requirement is met, the implementation process is simple, CPU intervention is not needed, dual-channel clock synchronization can be achieved only through an FPGA, and the implementation efficiency is improved. And the system complexity is reduced.

The invention relates to the technical field of integrated control systems, in particular to an integrated control system and method for hollow filter stick forming equipment, and the method comprises the steps: taking an embedded controller for running a real-time operating system as a control decision module, and carrying out the unified execution of all control algorithms; an Ethernet protocol with microsecond-level period and precise clock synchronization is used as a real-time communication module to form a system backbone network; the execution and acquisition layer integrates a motion control module composed of a servo driver and a motor as a network slave station, a signal interaction module composed of a distributed I / O module, and a subsystem integration module formed by bridging a third party subsystem through a communication gateway. According to the system, all key units are deeply integrated into the same real-time network as slave stations, so that centralized management, real-time synchronization and refined closed-loop control of the whole system are realized.

The invention relates to the technical field of integrated circuits and distributed computing, in particular to a chip computing network-oriented clock synchronization method, which is convenient for a receiving end to quickly identify and reduce analysis overhead by customizing a simplified synchronization frame format. A hardware synchronization module is deployed between a physical layer and a link layer to record a high-precision timestamp to eliminate an error caused by protocol stack processing, and a slave node calculates clock skew based on timestamp information interacted by a master node and a slave node and corrects the clock skew in real time to realize accurate synchronization. Master-slave roles are independently configured through each communication port, and automatic topology discovery is supported to adapt to a complex network structure. According to the method, an existing routing protocol and a physical link of the chip are reused, hardware overhead is reduced, synchronization precision is high, flexibility is high, the method can be widely applied to a computing network formed by an artificial intelligence acceleration chip graphics processor, a data processor and the like, and multi-chip cooperative computing efficiency and data consistency are effectively improved.

The invention relates to a clock management structure, a system on chip and electronic equipment, and the clock management structure comprises a phase-locked loop and an arbitration frequency division module connected with the phase-locked loop. The phase-locked loop is deployed in the PHY; the phase-locked loop is used for generating a phase-locked loop clock of X channels according to an externally input clock signal; the arbitration frequency division module is used for processing the phase-locked loop clocks of the X channels to generate an MAC interface clock, and synchronizing the MAC interface clock to an MAC interface and a port corresponding to each channel; wherein X represents the total number of channels corresponding to a plurality of ports between the PHY and the MAC. According to the clock management structure, the cross-clock domain design in the SoC design is greatly reduced, and the clock structure in the SoC is simplified, so that the area of the SoC chip is reduced.

The invention relates to the technical field of USB audio equipment optimization, and discloses a USB audio equipment Device mode implementation method and system, a storage medium and equipment, and the method comprises the steps: dynamically recognizing a connection type through detecting a USB data line voltage threshold value, and dynamically loading a corresponding protocol stack module based on the connection type; in a Device mode, a multi-stage buffer mechanism is adopted to manage audio data streams, the number and size of buffer areas are dynamically allocated according to target delay time, and clock synchronization with a host is realized based on an adaptive clock recovery algorithm; the power consumption of the equipment is dynamically adjusted through a multi-stage power consumption state machine, switching is carried out among working states according to an audio activity state and a data transmission requirement, and a remote wakeup function is supported; according to the method, a compatibility strategy library is matched based on a device fingerprint recognition result, protocol characteristics and audio formats of different host devices are automatically adapted, meanwhile, audio playing is controlled through audio quality monitoring and self-optimization, and Device mode support is added to the USB audio device through the method.

The present application relates to the technical field of autonomous driving. Disclosed are a clock synchronization system and method. In the system, a global synchronization module achieves clock synchronization of a global computing device on the basis of a clock signal of a navigation device, and sends to a local synchronization module a square wave signal including a timestamp. The local synchronization module completes, on the basis of the timestamp included in the square wave signal, the resetting for a system clock of the local synchronization module. The local synchronization module includes a plurality of local computing devices, wherein when capturing a rising-edge pulse signal, a first local computing device sends a trigger signal to a trigger-type sensor according to a set pulse width and starts timing, such that the trigger-type sensor transmits collected data to the first local computing device, and when a timing duration reaches a set threshold, the first local computing device stops sending the trigger signal; and a second local computing device uses a system clock thereof as a clock source of a non-trigger-type sensor connected thereto. The present application achieves high-precision clock synchronization without requiring gateway support.

Various aspects of the present disclosure generally relate to wireless communication. Some aspects more specifically relate to using one or more clock synchronization signals comprising sine waves to calibrate a local clock at an ambient internet of things (IoT) device. In some aspects, the ambient IoT device may receive a mixed signal comprising a pair of dual-tone sine waves and calibrate the local clock using a difference in frequencies of the pair of dual-tone sine waves.

The invention discloses a cascade clock synchronization circuit. The cascade clock synchronization circuit comprises M stages of clock synchronization circuits in cascade connection, and each clock synchronization circuit comprises a phase detection module and a clock generation module. When the i-th count value is X + 2N-1 and X + N-1, the phase detection module outputs an i-th phase detection signal and sets the i-th phase detection signal as an effective level; and the clock generation module carries out frequency division on the ith high-frequency clock N according to the effective level of the ith phase detection signal to generate an ith Nth frequency division clock synchronous with the ith high-frequency clock N, counts the level change of the ith-level phase detection signal to obtain an ith cascade count value, and outputs the ith-level cascade signal and sets the ith-level cascade signal as the effective level when the ith cascade count value is X + 2N-1 and X. According to the invention, the problem of synchronization failure caused by clock skew accumulation of the high-speed clock and the low-speed clock in the multi-channel clock synchronization process is solved. Especially in a multi-channel data synchronous transmission scene such as a multi-BANK multi-SerDes architecture, the problem of clock synchronization failure caused by clock skew accumulation is effectively solved.

The invention provides a clock synchronization method and a computer program product, and a sensing service control network element sends a first sensing request to a sensing data processing network element needing clock synchronization, so that the sensing data processing network element actively performs clock synchronization. And the sensing service control network element sends a second sensing request to the sensing equipment, so that the sensing equipment actively performs clock synchronization based on the target server selected by the sensing data processing network element. Therefore, in the multi-device cooperative sensing network, the client side can initiate the clock synchronization operation actively, so that the situation that devices which do not need to perform clock synchronization perform the clock synchronization operation is avoided, and the signaling expenditure of the whole network can be reduced.

The invention relates to the technical field of artificial intelligence control of a power supply system, in particular to an intelligent control method and system for the power supply system. The method comprises the following steps: acquiring data through a sensor after periodic calibration, and processing the data through a dynamic weighted fusion algorithm to obtain spatial-temporal characteristics; a reinforcement learning prediction model is used to predict based on a characteristic output working condition, a decision model is used to generate a control strategy, an instruction generated by decomposition of the control strategy is issued to an execution node after calculation power verification through dual-mode communication, and clock synchronization is maintained; the system calculates an execution state characterization value according to the execution state feedback, dynamically judges the control state of the power supply system, and then adaptively adjusts the calculation power verification period and the clock alignment period of the execution node based on the control state, thereby realizing the closed-loop optimization of system resource configuration and synchronization precision, and improving the control robustness and efficiency. According to the invention, the precision of adaptive control of the power supply system is improved.

The invention relates to a multi-module clock domain unification scheme based on second pulse calibration. The multi-module clock domain unification scheme comprises the steps that at a master control module end, an initial timestamp and a configuration instruction are issued to each slave module; generating a PPS signal meeting the precision requirement, and synchronously distributing the PPS signal to each slave module; at a slave module end, receiving the issued initial timestamp to configure a local clock; and receiving the PPS signal, and when the PPS signal is received, starting clock synchronization operation by using a master-slave module clock calibration algorithm to perform clock synchronization operation between the master module and the slave module.

Embodiments of this application provide a clock synchronization method and an apparatus. The clock synchronization method is applied to a slave node. The clock synchronization method includes: receiving a synchronization packet sent by a master node, where the synchronization packet carries a master clock timestamp of the master node; establishing a mapping relationship between a master clock of the master node and a reference timescale of the slave node based on the master clock timestamp and a timestamp corresponding to a reference timescale of the slave node when the slave node receives the synchronization packet; obtaining a time combination of the timestamp corresponding to the reference timescale of the slave node and slave clock time of the slave node, where a collection moment of the reference timescale of the slave node and a collection moment of the slave clock time corresponding to the reference timescale are the same.

The invention relates to the technical field of industrial automation control, and discloses a multi-station cooperative control method and system of a distributed PLC. The method comprises the steps that independent PLCs are arranged at feeding stations of an annular conveying line, and PLC control units are synchronously formed through an industrial Ethernet and a global clock; the order parameters and the target process information are written into a code carrier on the tray trolley through an RFID radio frequency read-write device, and the code carrier records the process progress, the detection result, the abnormal code and the beat deviation; when the code carrier enters each feeding station along with the tray trolley in sequence, the PLC control unit reads information, monitors the position of the trolley, executes a corresponding task and updates process information in real time; when the detection result is abnormal or the beat deviation exceeds a threshold value, the system triggers a beat adaptive algorithm to generate an optimization instruction set to guide the production beat adjustment; and the warehousing station combines the optimization instruction to execute finished product warehousing or repair processing. The automation level and the production efficiency of a production line are improved.

In one embodiments, a system includes a network device including a host interface to receive time synchronization messages generated by software executed by a processing unit of a host device, a hardware clock to maintain a clock time, scheduler circuitry to manage periodic transmission of the time synchronization messages according to the clock time and schedule data provided by the software, and a network interface to transmit the time synchronization messages to at least one clock synchronization follower according to the schedule data and the clock time.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a radio unit (RU) may synchronize a clock to a local synchronization source. The RU may send, to a distributed unit (DU), a notification to switch to a synchronization topology that includes the DU in a synchronization chain based at least in part on losing synchronization between the clock and the local synchronization source. The RU may receive timing information from the DU responsive to the notification. The RU may synchronize the clock to the timing information received from the DU. Numerous other aspects are described.

An application identifies a metadata field within a Remote Direct Memory Access (RDMA) message structure that can be used for timestamp injection. The application generates a high-resolution timestamp that captures a time when the RDMA message is sent, where the high-resolution timestamp has a first size that exceeds a size of the metadata field. The application compresses the high-resolution timestamp into a compressed timestamp having a second size that fits within the size of the metadata field, and injects the compressed timestamp into the metadata field of the RDMA message, the RDMA message sent from a sender host to a receiver host. The application calculates a one-way delay between the sender host and the receiver host using the compressed timestamp, and outputs a control signal based on the one-way delay.

The multifunctional control circuit comprises an FPGA (Field Programmable Gate Array) logic module, an LDO (Low Dropout Regulator) power supply module and a superconducting quantum computing chip which are in communication connection in sequence, the FPGA logic module comprises an AWG waveform memory, an AWG waveform playing controller, a bypass SFDR cancellation module and an RFSoC digital-to-analog conversion module which are in communication connection in sequence along the signal transmission direction, wherein the output end of the RFSoC digital-to-analog conversion module is set as the output end of the FPGA logic module; the FPGA logic module further comprises a clock synchronization module, and the clock synchronization module inputs a clock signal to the RFSoC digital-to-analog conversion module. According to the invention, the XY microwave pulse, the DC Pulse pulse and the DC Offset DC voltage are unified to be generated in the same FPGA and RFSoC architecture, the bypass SFDR cancellation module is added to generate a cancellation signal opposite to the phase of a spurious component, and the method has the advantages of significantly reducing the main spurious component in an output channel and improving the effective signal purity.

The invention belongs to the technical field of electronic measurement and control, and particularly relates to a seamless switching method for a VI source voltage range, and the system comprises a digital controller, a digital-to-analog converter, a programmable gain amplifier, an isolation switch module, a voltage maintaining and buffering module, a power amplifier, and a feedback measurement network. The digital controller is configured to receive a range switching instruction, manage the working state of the VI source, execute digital closed-loop voltage regulation and coordinate actions of all hardware components in the range switching process; a digital voltage reference generation module, a measuring range switching control logic module, a loop adjusting module and a high-precision clock synchronization unit are integrated in the digital controller. According to the invention, seamless switching of the output voltage can be realized, the test efficiency is obviously improved, the protection of the tested device is enhanced, and the data continuity and accuracy are improved.