687 results about "Clock synchronisation" patented technology

The invention discloses an audio synchronization output method and a system. The system comprises a control terminal, a media server and a plurality of play terminals which are accessed to a local area network. The method comprises the steps that S1, the control terminal selects one play terminal from the local area network to serve as a reference terminal, and sends a synchronization instruction to the reference terminal; S2, the reference terminal downloads specified audio information from the media server, decodes the audio information for generating digital audio information, and sends a clock synchronization coordination instruction to the specified play terminals, and the clock synchronization coordination instruction enables the play terminals to send clock synchronization coordination instruction return values to the reference terminal, and synchronizes a clock to the reference time; and S3, the reference terminal sends the digital audio information to the play terminals feeding back the clock synchronization coordination instruction return values within the required time for synchronously playing the digital audio information on the play terminals. Play time errors among the play terminals are reduced, and the quality of an audio is guaranteed.

The invention discloses a simulation system of simulating switched Ethernet clock synchronization. The simulation system comprises an Ethernet protocol instruction database, a timer, nodes, a link attribute configuration module, a synchronization topology generation module, a state management module, a state conversion module, a data processing module, a fault detection and processing module, a clock correction module and a result output module. The Ethernet protocol instruction database and the timer satisfy an IEEE802.3ISO/IEC8802-3 standard specification and instruction and state association information indicated in SAEAS6802. The nodes and the link attribute configuration module are used to carry out simulation role configuration so as to obtain a synchronization topology structure. Then, state role management is performed on each node in the synchronization topology structure and different state roles are used to carry out data processing, clock correction and fault detection. And then a state and clock correction result is output. Compared to the current simulation system, by using the simulation system of the invention, strong scalability is showed on an aspect of network model establishment, which is convenient to carry out an effective analysis on a clock synchronization process.

A timing circuit for use with transport logic in a network element is provided. The network element forms part of a data network and the timing circuit includes a timing receiver having a timing input, a timing output, and a selection input, the timing receiver operable to receive one or more timing signals at the timing input and to select a selected timing signal for distribution to the transport logic via the timing output based on a selection signal received at the selection input. The timing circuit also includes a determination circuit that is operable to determine whether the timing circuit is one of a master timing circuit and slave timing circuit, and based on the determination, produce the selection signal. A sync transmitter is also included in the timing circuit. The sync transmitter is coupled to the timing output, the determination circuit, and a communication channel. The sync transmitter is operable to receive the selected timing signal and to transmit the selected timing signal on the communication channel when the determination circuit determines that the timing circuit is the master timing circuit.

The invention discloses a multi-channel synchronous high-speed data collection device. A synchronous clock is provided through a clock management module, an ADC (Analog to Digital Converter) is driven by a sampling clock to sample a signal to obtain sampling data and then transmit the sampling data to an collection FPGA (Field Programmable Gate Array), a multi-ADC data synchronization module adds a timestamp mark for the sampling data in the ADC, the sampling data is subjected to sequence adjustment in the collection FPGA, a sampling point with a flag bit is adjusted to be a first path, and multi-ADC data stream synchronization is realized by increasing dynamic time delay; the clock synchronization timestamp adding and link establishment sequence management module manages the working sequence of three independent processes of clock synchronization, a timestamp function and a JESD204B link, and solves the conflict of the three independent processes in multi-ADC data synchronization, and the multi-channel sampling synchronization module adjusts the phase relation between a timestamp signal and a sending end device clock. The random delay caused by taking the time sequence of the two as an example is avoided, the accurate delay adjustment is performed on the signal based on the triggered data storage synchronization module, and the data synchronous storage between different boards is realized.

A clock-synchronized method for universal serial bus (USB) is described. The method includes the following steps of: (a) a transmitter sends a periodic signal to a host unit during a first time interval; (b) the host unit transmits a first equalization training sequence signal to a receiver during a second time interval to train the receiver and the transmitter continuously sends the periodic signal to the host unit; (c) a clock and data recovery device extracts the first equalization training sequence signal during the second time interval to generate a extracted clock signal and a data signal; and (d) the transmitter sends a second equalization training sequence signal to the host unit based on the extracted clock signal during the third time interval to train the host unit and the receiver and the transmitter commonly utilize the extracted clock signal as a reference clock.

A device that recognizes the time synchronization packet and substitutes a real-time value from the master internal counter into the proper place in a data packet is placed between an Ethernet Media Access Controller (MAC) and a Physical Interface Transceiver (PHY). A second device monitors the packet passing from the MAC to the PHY and determines when it is a time synchronization packet from the time master. Upon recognition of the proper packet, the second device simultaneously captures the master's time value and captures the value of a local real-time clock. The result of these captures are presented to the local host computer which controls the time base clock that increments the local real-time clock to either speed up or slow down this local clock, thereby synchronizing the local clock to the time master clock. The offset and skew of the local clock to the master clock is reduced to only the network latency plus variability due to network congestion.

The invention discloses a universal GPS indoor and outdoor positioning system and method. The universal GPS indoor and outdoor positioning system comprises a GPS pseudo satellite main station, three or more GPS pseudo satellite auxiliary stations, and a user receiver. The GPS pseudo satellite main station receives outdoor GPS signals in real time, acquires PPS (pulse per second) signal and a current visible satellite parameter, disciplines the clock of a local pseudo satellite main station by means of the PPS signal, synchronously generates two radiofrequency signals by means of a local disciplined clock, sends one radiofrequency signal to a user, and send the other radiofrequency signal to the GPS pseudo satellite auxiliary stations. The GPS pseudo satellite auxiliary stations receive signal sent from the GPS pseudo satellite main station, achieve synchronization between the local clocks of the GPS pseudo satellite auxiliary stations and the clock of the GPS pseudo satellite main station, and synchronously generate virtual GPS satellite simulating signals. The user synchronously receives the virtual GPS satellite signals sent from the visible pseudo satellite main station and pseudo satellite auxiliary stations and completes indoor and outdoor positioning of the user in real time. The universal GPS indoor and outdoor positioning system is simple and is not required to change the software and the hardware of a conventional GPS receiver.

The invention discloses an EtherCAT-based multi-axis synchronization control device, which comprises a mechanical body part, an AC servo driving part and a control part, wherein the mechanical body part comprises a support platform and a plurality of AC servo motors; the AC servo driving part comprises a plurality of AC servo driver slave stations in one-to-one corresponding connection with the AC servo motors; and the control part comprises a PC master station, which is in circuit connection with the AC servo driver slave stations by means of an EtherCAT network, and used for initializing the EtherCAT network, realizing master and slave clock synchronization of the PC master station and the AC servo driver slave stations as well as clock synchronization among the AC servo driver slave stations, and transmitting position signals to the AC servo driver slave stations. The invention further discloses an EtherCAT-based multi-axis synchronization control method. The EtherCAT-based multi-axis synchronization control device can realize the multi-axis synchronization control and signal acquisition based on an industrial Ethernet EtherCAT protocol.

An optical analog-digital converter with configurable frequency response sequentially comprises a controllable pulse shape optical sampling clock generating module, a repetition frequency doubling module, an electro-optical modulator, a multi-channel module, a photoelectric conversion module, an electric filter module, an electric analog-digital conversion module, a digital processing unit and a clock synchronization and aligning module. The optical analog-digital converter with configurable frequency response provides both analog processing and digitalization for broadband input microwave signals, system complexity is greatly reduced, and the problems, such as high insertion loss and signal distortion, due to respective filtration and sampling are avoided; system equivalent frequency response may be configured flexibly by adjusting time-domain shape of an optical sampling clock.

A DC mutual inductor check meter combining analog quantity and digital quantity verification functions comprises a main control module, an analog input sampling module, a digital quantity input parse module, a clock synchronization module, a man-machine exchange module, and a power supply module powering corresponding modules; the check meter also comprises following device interfaces: a clock synchronization interface, at least two analog input interfaces, and at least one digital quantity input optical network port; the analog input interfaces are connected with the analog input sampling module; the digital quantity input optical network port is connected with the digital quantity input parse module; the clock synchronization module is connected with the clock synchronization interface and the main control module; the main control module further processes the data sent by the analog input sampling module and the digital quantity input parse module, and processed data is sent to and displayed by the man-machine exchange module. The check meter can check the DC mutual inductors of either analog output type or digital quantity output type.

A method of synchronizing a clock for an adjacent network (AN) to a clock for an overlay network (ON) is provided. The method includes extracting an ON clock signal from an outgoing signal transmitted from the overlay network. The AN clock is synchronized to the ON clock based on the extracted ON clock signal.

The invention discloses a wireless sensor self-organized networking method comprising: self-defining a wireless sensor network networking protocol, transmitting a network command layer upon layer by broadcasting, completing a function of communication path storage during the process of broadcasting, completing a networking function. Based on a clock synchronization technology, the method implements simultaneous dormancy and simultaneous wakeup of the whole wireless sensor network, thus reducing efficiently power consumption in the wireless sensor network.

The invention provides a clock synchronization simplified information exchange method applied to a wireless sensor network. The method comprises steps: a cluster head side sends a message and records a time stamp t1, and a node side receives the message and records a time stamp t2; the node side sends and feeds back the message adn records a time stamp t3; the cluster head side receives the feedback message and records a time stamp t4; the cluster head side combines the time stamps t1 and t4 into a data packet and sends the data packets to the node side; according to the time stamps t2 and t3 and t1 and t4 analyzed from the data packet, the node side calculates clock offset for local clock calibration. The method is simple, synchronization time is greatly reduced, realization is convenient, an IEEE1588 accurate clock synchronization protocol and an IEEE802.15.4 wireless sensor network protocol are combined, at least two message sending and receiving times are saved during each time synchronization process, reliability is high, and the working efficiency is improved.

The invention discloses a network time synchronization device, system and method, the method includes following steps: step A: the business device sends the time request to at least one time sever at intervals of time; step B: compares the time samples returned by the time sever, choose the time sample to calculate the time difference between the local time and the time sever; step C: according to obtained time difference data to adjust the frequency regulator in the business device, and locks the time of superior time sever. Using the invention, it can obtain the time information of superior time sever via the transmission network, and according to the time information obtained in different time it can calculate the shift of local oscillator, and it can eliminate the local time shift by adjusting the frequency regulator to satisfy the requirement for the time of business device.

The invention discloses a control method of an Ethernet field-bus master station. The control method comprises an Ethernet field-bus master station structure and comprises the following detailed steps of: step a, carrying out initialization on the master station; step b, carrying out configuration on a slave station; step c, carrying out periodic data communication between the master station and the slave station; and step d, when aperiodic data needs to be processed, creating a protocol request and calling a reading or writing function of the protocol by the master station to acquire the aperiodic data. The invention has the beneficial effects that the real-time performance is obviously improved compared with that of the traditional EtherCAT soft and master station based on a Linux system; and by synchronization of the system time of the soft master station to the slave station, the clock synchronization between the master station and the slave station is improved, so that the real-time data interaction is better finished.

A mesh network system includes a plurality of network nodes, a network manager, and at least one access point. The network nodes communicate wirelessly with each other and the at least one access point of the mesh network system. The network manager manages operation of a wireless mesh network including the nodes and the at least one access point. The at least one access point communicates wirelessly with the network nodes, and provides a gateway between the wireless mesh network and the network manager. The at least one network access point is operative to synchronize its operation timing to an external clock, such as a UPS or UTC clock. Furthermore, in wireless mesh networks including multiple access points, the access points can synchronize their operation timing to each other, and can provide timing information to other access points and nodes in the network.

The present invention provides a semiconductor integrated circuit device realizing improved detection of a failure while suppressing deterioration in performance. In a semiconductor integrated circuit device executing a plurality of threads while switching them synchronously with clocks, registers used for executing the threads are provided for the respective threads. Programs independent of each other and the same program as the threads are executed while being switched. In the case of executing the same program by a plurality of threads, a comparison circuit for comparing results of execution using registers provided in correspondence with the threads is provided.