2results about How to "Avoid buffering" patented technology

This invention discloses a digestion apparatus for determining the content of polyisoprene, comprising a steam generating flask, with a conduit connected to the top of the steam generating flask, and a Claisen inductor connected to the end of the conduit away from the steam generating flask. This digestion apparatus provides a reaction site through the steam generating flask, generating stable steam, which is then provided with a uniform heat source via a heating seat to accelerate sample digestion and prevent localized overheating. The steam is then introduced into the Claisen inductor via the conduit. The Claisen inductor enables multifunctional connections, preventing sample loss, improving reaction efficiency, providing safety protection, preventing harmful gas leakage, improving reaction control precision, and ensuring optimal experimental conditions. The digestion flask provides a sealed, high-temperature and high-pressure resistant reaction environment, promoting the complete decomposition of organic matter in the sample and ensuring reaction uniformity and safety.

The invention relates to the field of signal processing and the technical field of semiconductor integrated circuits, in particular to a storage and calculation integrated MIMO precoding circuit, a storage and calculation integrated MIMO precoding method, an operation framework and a communication system. Comprising two groups of novel memory arrays, an operational amplifier, a voltage phase inverter, a current phase inverter and a trans-impedance amplifier, the first novel memory array comprises a first sub-array, a second sub-array and a third sub-array, and the second novel memory array comprises a fourth sub-array and a fifth sub-array; the second sub-array is connected with the third sub-array through the voltage phase inverter, and the fifth sub-array is connected with the trans-impedance amplifier through the current phase inverter. The two novel memory arrays cooperatively work in the same analog calculation loop, so that the circuit directly outputs a pre-coding result in a steady state, and sampling hold, interface buffer and additional control logic required by cascade connection of multi-stage modules in the prior art are avoided, thereby reducing system time delay and power consumption overhead.