A reconfigurable 
data path processor comprises a plurality of independent 
processing elements. Each of the 
processing elements advantageously comprising an identical architecture. Each 
processing element comprises a plurality of 
data processing means for generating a potential output. Each processor is also capable of through-putting an input as a potential output with little or no processing. Each 
processing element comprises a conditional 
multiplexer having a first conditional 
multiplexer input, a second conditional 
multiplexer input and a conditional multiplexer output. A first potential output value is transmitted to the first conditional multiplexer input, and a second potential output value is transmitted to the second conditional multiplexer output. The conditional multiplexer couples either the first conditional multiplexer input or the second conditional multiplexer input to the conditional multiplexer output, according to an output control command. The output control command is generated by processing a set of arithmetic status-bits through a logical 
mask. The conditional multiplexer output is coupled to a first 
processing element output. A first set of arithmetic bits are generated according to the processing of the first processable value. A second set of arithmetic bits may be generated from a second processing operation. The selection of the arithmetic status-bits is performed by an arithmetic-status bit multiplexer selects the desired set of arithmetic status bits from among the first and second set of arithmetic status bits. The conditional multiplexer evaluates the select arithmetic status bits according to logical 
mask defining an 
algorithm for evaluating the arithmetic status bits.