Fractional-N frequency synthesizer with jitter compensation

Abstract

A fractional-N frequency synthesizer has a VCO with an output for supplying an output signal of a particular frequency, and an input for receipt of a control signal for controlling the operation of the VCO so that it locks in on a reference frequency. Compensation circuitry is coupled to the input for compensating the output signal for phase jitter. The compensation circuitry has a charge pump that supplies a compensation current to the input. The timing is derived from the output signal, thus rendering the compensation current independent of the frequency range of the VCO and of the reference frequency.

Description

The invention relates to an electronic device that has a fractional-N frequency synthesizer with compensation circuitry to compensate for phase jitter. The device comprises, e.g., an integrated circuit or a digital communication apparatus. The invention also relates to a method of compensating phase jitter in a fractional-N frequency synthesizer.A frequency synthesizer creates multiple output signals, each with a different frequency, from a reference signal that has a highly stable reference frequency. The reference signal is generated by a crystal oscillator. Typically, a synthesizer comprises a voltage controllable oscillator (VCO) in a phase-locked-loop (PLL). The PLL controls the oscillator to keep the frequency and phase of the oscillator's output signal locked to those of the reference signal. The PLL has a phase detector to compare the phase of the oscillator's output signal with the phase of the reference signal. The detector controls a charge pump that supplies an error sig...

AI Technical Summary

Benefits of technology

The known current compensation scheme functions well, but depends on the chosen reference frequency and on the frequency at which the VCO is supposed to operate. This demands that the compensating pump producing the compensation current is required to operate over a range of current densities that depends on the chosen frequencies. In other words, t

Problems solved by technology

However, lowering the bandwidth also increases the settling time that is needed for the PLL to lock in on the reference signal.

Division by N+1 requires one more input cycle than dividing by N. The result is a pe