Integration of ALD tantalum nitride and alpha-phase tantalum for copper metallization application

Abstract

A method for forming a metal interconnect on a substrate is provided. The method includes depositing a refractory metal-containing barrier layer having a thickness less than about 20 angstroms on at least a portion of a metal layer by alternately introducing one or more pulses of a metal-containing compound and one or more pulses of a nitrogen-containing compound. The method also includes depositing a seed layer on at least a portion of the barrier layer, and depositing a second metal layer on at least a portion of the seed layer. The barrier layer provides adequate barrier properties and allows the grain growth of the metal layer to continue across the barrier layer into the second metal layer thereby enhancing the electrical performance of the interconnect.

Description

[0001] This application claims benefit of U.S. Provisional Patent Application Serial No. 60 / 346,086, filed on Oct. 26, 2001, and entitled "Method and Apparatus for ALD Deposition", which is incorporated by reference herein. This application also claims benefit of U.S. patent application Ser. No. 09 / 965,370, filed on Sep. 26, 2001, and entitled "Integration of Barrier Layer and Seed Layer", which is incorporated by reference herein. This application also claims benefit of U.S. patent application Ser. No. 09 / 965,373, filed on Sep. 26, 2001, and entitled "Integration of Barrier Layer and Seed Layer", which is incorporated by reference herein. This application also claims benefit of U.S. patent application Ser. No. 09 / 965,369, filed on Sep. 26, 2001, and entitled "Integration of Barrier Layer and Seed Layer", which is incorporated by reference herein.[0002] 1. Field of the Invention[0003] Embodiments of the present invention relate to a method for manufacturing integrated circuit device...

AI Technical Summary

Problems solved by technology

However, copper diffuses more readily into surrounding materials and can alter the electronic device characteristics of the adjacent layers and, for example, form a conductive path between layers, thereby reducing the reliability of the overall circuit and may even result in device failure.

Therefore, the additional amount of the barrier layer on the bottom of the feature not only increases the overall resistance of the feature, but also forms an obstruction between higher and lower metal interconnects of a multi-layered interconnect structure.

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