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Multimedia jitter removal in an asynchronous digital home network

A technology for multimedia data and data frames, which is applied in data exchange networks, digital transmission systems, synchronization devices, etc.

Inactive Publication Date: 2004-08-18
THOMSON LICENSING SA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, such methods are not well suited for correcting jitter in asynchronous collision detection networks such as Ethernet

Method used

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  • Multimedia jitter removal in an asynchronous digital home network
  • Multimedia jitter removal in an asynchronous digital home network
  • Multimedia jitter removal in an asynchronous digital home network

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0026] figure 2 A digital home network using time stamping according to the invention is shown. The wideband input signal is provided by a headend (not shown) and received by wideband receiver / multimedia server 202 . Server 202 may be configured to receive said input from one of a plurality of broadband sources such as satellite, cable or DSL as indicated by inputs Sys1, Sys2...Sysn. This input signal may be in the form of transport packets that include System Clock Recovery (SCRs) information used by the receiver 202 to frequency lock its local system clock to the headend system clock. The SCRs are used to manage buffering levels and to derive video timing and burst signals in the Integrated Receiver Decoder (IRD). Importantly, in order for the system 200 to work correctly, the entire system 200 must maintain the relationship between SCR information and message packet timing from the beginning of entering the network to the final presentation point.

[0027] Data received...

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PUM

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Abstract

A method and an apparatus using a system level clocking scheme to remove jitter from multi-media packets distributed over an asynchronous network, in particular an Ethernet network. The present invention overcomes the problems associated with jitter introduced in an Ethernet network by using various time stamps to synchronize a client device clock to a headend clock and to control the data flow in the client device to match the rate that the data is received by a broadband receiver coupled to the headend. A first time stamp is prepended to the transport packets when the packets are received from the headend. A second time stamp is placed in the data frame when the data frame is placed on the network. A third time stamp is placed in the data frame when the data frame is received from the network. The second and third time stamps are used for clock synchronization and the first time stamp is used for data flow control. According to the present invention, the time stamps are added at the physical layer so that the time stamps correspond to the actual time the data packets are placed onto and received from the asynchronous network.

Description

technical field [0001] The present invention relates to asynchronous communication networks, and more particularly to asynchronous multimedia digital home networks with system-level synchronization schemes to remove jitter from multimedia data packet packets. Background technique [0002] New developments in digital communication technologies have increased the viability of digital home networks ("DHNs"), which allow various devices in the home to communicate with each other. In particular, the ever-increasing availability of broadband access makes it possible to count on connecting various devices in a home to a single gateway device coupled with broadband access for centralized access and distribution of multimedia information. In such a digital home network, a gateway device accesses and caches multimedia content and transmits the content over the network when requested by various client devices coupled to the network. [0003] Ethernet is a common choice for implementin...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/56H04J3/06H04L7/00
CPCH04J3/0673H04L65/00H04L29/06523H04N21/4305H04J3/067H04L29/06176H04J3/0664H04L65/80H04L12/28
Inventor 丹尼尔·T·韦策尔安·Q·古延
Owner THOMSON LICENSING SA
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