Clock and data recovery circuit

Abstract

A clock and data recovery circuit, for tracking frequency-modulated input data, comprises a phase detector for receiving a data signal and a synchronous clock signal, detecting a phase delay or a phase advance, and outputting an UP1 / DOWN1 signal, first and second integrators for integrating the UP1 / DOWN1 signal and outputting an UP2 / DOWN2 signal and an UP3 / DOWN3 signal, respectively, a pattern generator for receiving the UP3 / DOWN3 signal from the second integrator to output an UP4 / DOWN4 signal, a mixer for receiving the UP2 / DOWN2 signal from the first integrator and the UP4 / DOWN4 signal from the pattern generator and generating an UP5 / DOWN5 signal for output, and a phase interpolator for interpolating the phase of an input clock signal based on the UP5 / DOWN5 signal from the mixer, for output are provided. A clock signal output from the interpolator is fed back to the phase detector as the clock.

Description

[0001] The present invention relates to a clock and data recovery circuit for generating a clock signal and data from input data.[0002] When a clock generator in an electronic device generates a single frequency, emission increases due to the frequency and harmonics. Thus, a spread spectrum clock signal for reducing electromagnetic interference by performing frequency modulation and thereby reducing peaks of unwanted emissions is employed. As an approach for extracting a clock signal from serial data frequency modulated using the spread spectrum clock, a clock and data recovery circuit as shown in FIG. 13 is known (refer to Non-patent Document 1, for example).[0003] Referring to FIG. 13, in addition to a phase tracking loop constituted from a phase detector 201, an integrator 202, and a phase interpolator 206, a frequency tracking loop constituted from an integrator 203, a charge pump 214, a loop filter 215, a VCO (voltage controlled oscillator) 216, and the phase interpolator 206 i...

AI Technical Summary

Benefits of technology

[0016] The clock and data recovery circuit having the frequency tracking loop including the charge pump 214, loop filter 215, and VCO 216 can be configured to track frequency modulation exceeding 0.5%. However, when the clock and data recovery circuit is made to have a multi-channel configuration, the chip size and power consumption increases. It means that when the clock and data recovery circuit having the frequency tracking loop including the charge pump, loop filter, and VCO (voltage controlled oscillator) is made to have the multi-channel configuration, all channels will be equipped with frequency tracking loops each including the charge pump, loop filter, and VCO, thereby increasing the chip size. Then, if high-speed VCOs are provided for all channels in a high-speed system of 1 Gbps or higher, for example, power consumption will increase.

[0017] Accordingly, it is an object of the present invention to provide a clock and recovery circuit with a reduced circuit size, which can track frequency-modulated input data while effecting reduction in chip size and reduction in power consumption.

[0018] The inventor of the present invention, as a result of having made an intensive study to solve the problems described before, has found that, by disposing a phase interpolator for adjusting the phase of an output clock signal based on a control signal, providing in a frequency tracking loop a pattern generator for generating a control signal for frequency tracking as necessary based on the result of phase comparison and synthesizing an up / down signal of a phase tracking loop and an up / down signal from the pattern generator in the frequency tracking loop to supply the synthesized signal to the phase interpolator as a control signal, a clock and data recovery circuit with a reduced circuit size can be implemented without using a VCO.

Problems solved by technology

However, when the clock and data recovery circuit is made to have a multi-channel configuration, the chip size and power consumption increases.

Then, if high-speed VCOs are provided for all channels in a high-speed system of 1 Gbps or higher, for example, power consumption will increase.

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