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Soft reset device of integrated circuit chip

An integrated circuit and soft reset technology, applied in the direction of electrical pulse generator circuits, logic circuits to generate pulses, electrical components, etc., can solve problems such as inability to clear register data content, inability to integrate chips, abnormal chip identification, etc., to achieve design Clear thinking, area saving, good achievability

Inactive Publication Date: 2008-03-12
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Traditional chip reset circuits are generally made in an off-chip environment, including soft or hard reset circuits. This kind of reset circuit has only one reset function, and it is not sure whether to clear the data content in the register; at the same time, because the chip reset process includes: The chip identification is abnormal; the external command is issued and the chip itself is ready for reset; the external soft reset circuit receives the command and delays according to the specific reset preparation needs of the chip and then sends out a reset signal; in this way, the reset speed is slow and the power consumption is large, so it cannot be integrated into the chip. Inside, it is not suitable for the rapid development of integrated circuit applications at this stage, the reset preparation is used to save the necessary register status or data

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Embodiment Construction

[0029] At first, the device of the present invention is described:

[0030] What Fig. 1 shows is the soft reset device circuit structure that the present invention provides, and it mainly has three components: (one) oscillator 11 and bias circuit thereof, (two) first edge detection unit 12 and bias circuit thereof , (3) Resetting the module 13 . Among them, the oscillator can be designed with a large phase shift, and even weak noise can generate oscillation. An input enable port EN is set, and the output signal port of the oscillator is SWRESET, which outputs a reset pulse signal. The next reception is the edge detection unit, the input is the SWRESET signal, and the module output signal is the SWRST_CLR_B signal. The edge detection unit monitors the change of the SWRESET signal and gives a reset end signal at the SWRST_CLR_B signal end; the next reception is the reset module, and the input signal is SWRST_CLR_B, the output is reset to close the Disable and RESET signal, and ...

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PUM

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Abstract

The invention relates to a soft reset device for integrated circuit chip and is inserted into the integrated circuit chip. The utility model consists of a ring shape oscillator(11), a reset pulse signal that has certain cycle and meets the reset request under the action of trigger signal according to the software control; a first edge detecting unit(12) that receives the reset pulse signal and outputs reset ending signal, a reset module(13) that receives the reset ending signal and outputs reset signal to start-up reset while outputs reset closing signal to the ring shape oscillator to stop the output of the reset pulse signal. The static power consumption of the module is around zero; the area is small and can prevent the filtering of high frequency input signal caused by the low pass property of the RC; compatible to meet more than one trigger method; clear design concept and can be realized by standard CMOS technique approved by tape-out inspection needless of adding mask.

Description

technical field [0001] The invention relates to integrated circuits, in particular to a soft reset device for integrated circuit chips. Background technique [0002] With the extensive development of CMOS integrated circuits, integrated circuit chips work at faster and faster speeds, which puts forward higher and higher requirements for the clock signal that drives the entire circuit. For high-speed digital circuits operating at a frequency of hundreds of megahertz, the stability of the clock signal directly affects whether the circuit can work normally. When the high-frequency signal is transmitted, affected by stray distributed capacitance, inductance, etc., the distortion and drift of the clock signal seriously affect the precise operation of the circuit with the clock. Integrated circuits often need a reset circuit, which can automatically reset the chip when the system enters an error working mode, but it does not need to turn off the power or reset to clear all the da...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K17/22H03K5/1534H03K3/03
Inventor 王洋
Owner ZTE CORP
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