Method of decomposing integrated circuit layout and computer readable media

Abstract

The invention relates to a method of decomposing the integrated circuit layout and the computer readable media storing a plurality of computer instructions. Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout library as inputs wherein the library provides exemplary layouts that have been verified to be spit-able and that can be used and layouts that can cause conflicts to avoid. A real-time odd cycle checker is also provided in which the checker identifies in real time conflict areas and odd cycles as they arise during layout generation. To reduce memory usage layouts of various devices may be separated so that each individual layout or a small number of layouts, rather than a large layout for the whole application circuit, can be checked against conflicts. Once the layout is ready at the customer site, it is sent to the foundry site to be decomposed into two masks and taped-out. Other embodiments are also disclosed.

Description

technical field [0001] Embodiments of the invention generally relate to integrated circuit layouts. Mechanisms provided in various embodiments of the present invention enable layouts to meet double patterning requirements, including separation of layouts into different reticles. Background technique [0002] If the layout of the integrated circuit includes conflicting loops, it cannot be separated into two reticles. A conflict cycle may be called an odd cycle because it is a cycle in a conflict graph that contains odd edges. Many layout designers (eg, semiconductor foundry customers) do not have the tools to check for those conflicting loops, and thus may violate the rules for separate placement. Many layout methods cannot fix odd loops and related problems because of constraints on joint locations. A straightforward approach is to split the pattern, connect the polygons by joint regions, and use a matrix global solver to decompose the layout. However, this approach cons...

AI Technical Summary

Problems solved by technology

However, this method consumes massive memory and increases cycle time, and the customer is generally not involved in the layout making process, which is inconvenient for the user because different methods are used to decompose the layout when polygons are cut or not cut

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