Processor with polymorphic instruction set architecture

An instruction processing and set system technology, applied in the direction of concurrent instruction execution, machine execution devices, etc., can solve the problem of unable to redefine the processor instruction set, and achieve the effect of improving processing performance

Active Publication Date: 2013-08-07
BEIJING SMART LOGIC TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0011] The technical problem to be solved by the present invention is to propose a processor with a polymorphic instruction set architecture to solve the problem that the processor cannot redefine the processor instruction set after tape-out

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  • Processor with polymorphic instruction set architecture
  • Processor with polymorphic instruction set architecture
  • Processor with polymorphic instruction set architecture

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Embodiment Construction

[0039] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0040] The present invention proposes a processor capable of dynamically reconfiguring a polymorphic instruction set architecture after tape-out (trial production).

[0041] The structure of the processor of the present invention is as figure 1 As shown, it mainly includes the following components: a scalar processing unit 101 , at least one polymorphic instruction processing unit 100 , at least one multi-granularity parallel memory 102 and a DMA controller 103 . The polymorphic instruction processing unit 100 includes at least one functional unit.

[0042] The polymorphic instruction refers to a sequence of multiple consecutively executed microcode records. The polymorphic instruction set is a collection of polymorphic...

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Abstract

The invention provides a processor with a polymorphic instruction set architecture. The processor comprises a scalar processing unit (101), at least one polymorphic instruction processing unit (100), at least one multi-granularity parallel memory (102) and a direct memory access (DMA) controller (103). Each of the polymorphic instruction processing units (100) comprises at least one function unit (202), the polymorphic instruction processing units (100) are used for explaining and executing polymorphic instructions, and the function units (202) are used for executing specific data operation tasks; the scalar processing unit (101) is used for calling the polymorphic instructions and inquiring execution states of the polymorphic instructions; and the DMA controller (103) is used for transmitting configuration information of the polymorphic instructions and transmitting data required by the polymorphic instructions to the multi-granularity parallel memories (102). According to the processor, programmers can still redefine the instruction set of the processor according to characteristics of an application algorithm after tape-out production of the processor.

Description

technical field [0001] The present invention mainly relates to the processor instruction set architecture, which is closely related to the definition of the processor instruction set, the design of the processor architecture and the implementation method of the micro-architecture, especially a polymorphic instruction that can be dynamically reconfigured after tape-out processor set architecture. Background technique [0002] In recent years, the Internet, cloud computing, and the Internet of Things have developed rapidly. Ubiquitous mobile devices, RFID, and wireless sensors are generating information every second, and hundreds of millions of users of Internet services have generated a huge amount of information interaction; at the same time, users have put forward high requirements for the real-time and effectiveness of information processing , such as an online video-on-demand system, users not only require high-definition images, but also require decoding and display spe...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38G06F9/30
Inventor 王东琳谢少林杨勇勇尹磊祖王磊刘子君汪涛张星
Owner BEIJING SMART LOGIC TECH CO LTD
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