Method for realizing heterogeneous many-core of sparse matrix-vector multiplication based on domestic SW26010 processors

Abstract

The invention discloses a method for realizing heterogeneous many-core of sparse matrix-vector multiplication based on domestic SW26010 processors. As the non-zero elements of a sparse matrix are distributed very irregularly, two different static and dynamic task partitioning methods are designed in the method, so as to adapt to different sparse matrices; a set of dynamic and static cache mechanism is provided, so as to promote the memory access hit rate of a vector x; a set of self-adapting optimization method is provided, specific to the sparse matrix, the optimal execution parameters can be dynamically selected, so as to promote the running performance. According to the method disclosed by the invention, 16 sparse matrices in a Matrix Market matrix set are adopted to conduct test, the running edition SpMV has about 10 times of acceleration to the utmost extent compared with the single main core of a domestic SW processor, and the average speed-up ratio is 6.51.

Description

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AI Technical Summary

Benefits of technology

This patented technology allows for better resource management by dividing tasks into smaller parts based upon their characteristic values instead of relying solely on previous techniques like assigning or randomizing resources. By doing that, system efficiency increases while reducing unnecessary workload. Additionally, the spaware approach uses sparse data elements without storing them locally has lower latency than traditional approaches due to its location within an image processing unit (GPU). Overall, these technical improvements help optimize both hardware usage and software applications running at GPUs.

Problems solved by technology

This patented technical solution describes various techniques for efficiently performing computations involving multiply data streams called sparsity or sparse matrices. One technique uses algorithms like convolution decomposition, random field approximation, linear programming, etc., while another method includes decomposable multidimensional mapping and advanced modulation systems. Additionally, certain methods aim at reducing memory access latency without sacrificializing thread execution capabilities. Overall, both types of solutions provide benefits over conventional approaches due to their ability to optimize resource allocation and minimize interference during computation.

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