System and method for dispatching FPGA (Field Programmable Gate Array) accelerator based on Xen virtualized cluster

Abstract

The invention relates to a system and a method for dispatching an FPGA (Field Programmable Gate Array) accelerator based on a Xen virtualized cluster. The system comprises multiple servers, wherein the servers are mutually connected through an exchanger to form a cluster; each server comprises a privileged domain virtual machine, multiple non-privileged domain virtual machines and an FPGA; the privileged domain virtual machine is respectively in communication with the multiple non-privileged domain virtual machines and the FPGA; the multiple non-privileged domain virtual machines share the FPGA through the privileged domain virtual machine; the privileged domain virtual machine in each server is in communication with the privileged domain virtual machines in other servers through a network card. Compared with the prior art, the system and the method, disclosed by the invention, have the advantages that the equipment utilization rate is increased, the equipment cost is reduced, and the like.

Description

Technical field [0001] The invention relates to a scheduling system, in particular to an FPGA accelerator scheduling system and method based on Xen virtualized clusters. Background technique [0002] With the continuous development of technology, although the running speed of software continues to increase, compared with directly implementing its functions with hardware, software is far inferior to the processing speed of hardware when processing complex and computationally intensive algorithms. At present, some functional modules in wireless communication such as Turbo decoding, FFT, etc., the algorithm time complexity is very high, the calculation amount is large, resulting in a long response time, the use of hardware accelerators instead of computing-intensive software code, directly on the hardware device Turbo decoding, FFT and other processing can effectively increase the processing speed and shorten the response time. We use flexible FPGAs to accelerate complex algorithm ...

AI Technical Summary

Problems solved by technology

[0002] With the continuous development of technology, although the running speed of software continues to increase, compared with directly realizing its functions with hardware, software is far behind the processing speed of hardware when dealing with high-complexity and calculation-intensive algorithms.

At present, some functional modules in wireless communication, such as Turbo decoding, FFT, etc., have high algorithm time complexity and a large amount of calculation, resulting in a long response time. Hardware accelerators are used instead of computationally intensive software codes, which are directly implemented on hardware devices. Turbo decoding, FFT and other processing can effectively improve the processing speed and shorten the response time

We choose flexible FPGA to realize the acceleration of complex algorithm functions, but the hardware equipment is generally expensive, and each host occupies a piece of equipment, which not only costs high, but also leads to low equipment utilization and serious waste of resources

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