Xen-based FPGA accelerator virtualization platform and application

A virtualization platform and accelerator technology, applied in software simulation/interpretation/simulation, program control devices, etc., can solve problems such as low utilization efficiency, inability to overcome response speed, and limited improvement of FPGA hardware speed, so as to reduce computing time, Effects of improving access speed, computing efficiency, and communication efficiency

Active Publication Date: 2016-03-09
TONGJI UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Since FPGA has the characteristics of fast running speed, large-scale system implementation, strong computing power, and convenient secondary development, it is widely used in wireless communication systems. At present, most researches focus on the design of FPGA accelerators. However, FPGA hardware speed The improvement level is limited, the cost is high, and when multiple users use an accelerator at the same time, the problems of slow response and low utilization efficiency cannot be overcome

Method used

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  • Xen-based FPGA accelerator virtualization platform and application
  • Xen-based FPGA accelerator virtualization platform and application
  • Xen-based FPGA accelerator virtualization platform and application

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Experimental program
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Embodiment 1

[0041] Using FPGA, that is, Field Programmable Gate Array, you can burn your own designed logic circuits, such as accelerator logic functions, into it for strong adaptive function realization. In this embodiment, Xen is used to virtualize the FPGA, so that multiple users can simultaneously use the same FPGA to perform accelerated operations, improve hardware utilization efficiency and user response speed, and make full use of hardware resources.

[0042]A Xen-based FPGA accelerator virtualization platform that uses FPGA hardware to calculate some modules in wireless communication to achieve hardware acceleration. At the same time, users are placed in a virtual machine based on Xen, and through the method of hardware device virtualization, multiple users can use hardware computing at the same time to improve the efficiency of hardware usage. like Figure 1~2 As shown, the platform includes a virtual machine module 1 and an FPGA module 4 connected to each other. The virtual mac...

Embodiment 2

[0049] A kind of application of the FPGA accelerator virtualization platform based on Xen as described in embodiment 1, such as image 3 shown, including the following steps:

[0050] S01, build the described Xen-based FPGA accelerator virtualization platform;

[0051] S02, the user space in the user virtual machine sub-module 11 generates a hardware accelerator use request, specifically: the user space accesses the hardware accelerator through a program to perform a write operation, and calls the virtual front-end driver 111 in the kernel of the user virtual machine sub-module 11;

[0052] S03, the virtual front-end driver 111 sends the hardware accelerator use request to the virtual back-end driver 121 by using the event channel, authorization table and shared ring mechanism of Xen;

[0053] Step S03 specifically includes the following steps:

[0054] S0301, the virtual front-end driver 111 registers and initializes, allocates authorization table memory, establishes a shar...

Embodiment 3

[0068] Embodiments 1 and 2 are specifically applied to an actual FPGA accelerator.

[0069] In Xen, the Xenhypervisor is at the bottom and is the most privileged software layer. Multiple GuestOS (sub-operating systems) are supported through this layer, which is responsible for scheduling physical CPUs. The first GuestOS to start is Domain0 (Dom0), which has management rights and direct access to hardware resources. The system administrator can log in to Domain0 to manage other GuestOS, that is, user-level DomainU (DomU).

[0070] The communication mechanism between Dom0 and DomU mainly includes shared ring, event channel and authorization table. The I / O sharing ring transmits I / O requests and responses between Dom0 and DomU through a fixed memory. The event channel is used for asynchronous notification between Doms and Xen. The authorization table can map memory pages from one Dom to another Dom, and use the page mapping shared memory mechanism of the authorization table t...

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Abstract

The present invention relates to a Xen-based FPGA accelerator virtualization platform and application. The Xen-based FPGA accelerator virtualization platform is characterized by comprising a virtual machine module (1) and an FPGA module (4) connected with each other. The virtual machine module (1) comprises a user virtual machine submodule (11), a privileged virtual machine submodule (12) and a data transmission module (13); the user virtual machine submodule (11) is provided with a virtual front-end driver (111); the privileged virtual machine submodule (12) is provided with a virtual back-end driver (121) and an actual driver (122); the virtual front-end driver (111) is connected to the virtual back-end driver (121) through the data transmission module (13); the actual driver (122) is connected to the FPGA module (4); and both the virtual front-end driver (111) and the actual driver (122) realize character device virtualization through a Xen. Compared with the prior art, the Xen-based FPGA accelerator virtualization platform disclosed by the present invention enables multiple users to simultaneously use the accelerator, thereby improving access speed and computational efficiency.

Description

technical field [0001] The invention relates to an FPGA accelerator virtualization platform and an application, in particular to a Xen-based FPGA accelerator virtualization platform and an application. Background technique [0002] In a wireless communication system, multiple modules require a relatively long period of operation to obtain results, and these operations affect the efficiency of communication, so how to shorten the operation time to improve communication efficiency is an important issue. Computing such as FFT module, Turbo decoder module, MIMO equalizer module, etc. through hardware can increase the computing speed, improve communication efficiency, and can also flexibly use some corresponding modules to quickly complete tasks. Since the speed of hardware is greatly improved compared with software, and the cost of hardware resources is relatively high, it is necessary to make full use of hardware resources. [0003] FPGA (Field-Programmable GateArray), that is...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/455
Inventor 吴俊汤绍先朱慧郭栋石丰略苏立峰
Owner TONGJI UNIV
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