Winograd YOLOv2 target detection model method based on FPGA acceleration

Abstract

The invention discloses a Winograd YOLOv2 target detection model method based on FPGA acceleration. The method comprises the steps: employing a PYNQ board card, and enabling a main control chip of thePYNQ board card to comprise a processing system end PS and a programmable logic end PL; wherein the PS end caches a YOLO model and feature map data of a to-be-detected image; the PL end caches the parameters of the YOLO model and the to-be-detected image into an on-chip RAM, deploys a YOLO accelerator with a Winograd algorithm, completes acceleration operation on the model, forms a data path of ahardware accelerator, and realizes target detection of the to-be-detected image; and an operation result of the acceleration circuit can be read out, and image preprocessing and display are carried out. By adopting the technical scheme of the invention, the calculation complexity of the YOLO algorithm can be reduced, the FPGA accelerator storage optimization algorithm reduces the calculation timeof the FPGA when accelerating the YOLO algorithm, accelerates the target detection, and effectively improves the performance of the target detection.

Description

technical field [0001] The invention belongs to the technical field of computer vision and edge computing, and relates to an FPGA accelerator design method for a target detection model. Background technique [0002] In recent years, with the development of machine vision and edge computing, the network model of target detection and recognition based on deep learning network has been greatly developed, and has achieved a lot in the fields of video scene monitoring, robot control, and unmanned vehicles. Applications. Representative models include single-shot-multibox-detection (SSD), FasterR-CNN, and you-only-look-once (YOLO network model) series. Among them, the YOLO algorithm has faster and more accurate performance advantages. [0003] Most of the target detection and recognition models based on deep learning networks are completed in Graphic Processing Units (GPUs). The performance advantages are more prominent. However, edge computing needs to run on computing devices ...

AI Technical Summary

Problems solved by technology

However, in the existing accelerator design methods, there are many problems such as unreasonable on-chip resource allocation and high power consumption. Therefore, it is a very challenging technical task to realize the high-efficiency and low-power inference of the target detection model in FPGA.

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