85results about How to "Accelerated implementation" patented technology

The embodiment of the invention discloses a decompression method, device and system for an FPGA heterogeneous acceleration platform. The method comprises the following steps: receiving first data to be decompressed sent by a host side processor and storing the first data to be decompressed; calling a decompression algorithm implemented by an FPGA hardware circuit according to a start-up instruction and parameter information sent by the host side processor, and decompressing the first data to be decompressed based on the decompression algorithm to obtain decompressed data, wherein the parameter information contains data information corresponding to the first data to be decompressed and a compression relation table; and storing the decompressed data, and returning a completion signal to the host side processor to ensure that the host side processor receives the completion signal and then reads the decompressed data. According to the decompression method, device and system disclosed by the invention, the decompression speed can be increased during use, and the power consumption required during decompression can be reduced.

The invention discloses a convolution nerve network acceleration method based on pre-deciding, comprising steps of obtaining a calculation price of each characteristic point and dependency relation between the characteristic points according to the characteristics that CNN forward propagation and each layer calculation mode, establishing a characteristic point selection model on the basis of the calculation price of each characteristic point, the dependency relation between the characteristic points and the classification capability of the characteristic point, configuring a series of incremental characteristic point quantities according to the structure characteristic points, using the characteristic point selection model to perform one-by-one optimization on the series of incrementing characteristic point number according to a training data set which is established in advance to obtain linearity classifiers which are chosen by and corresponding to the series of characteristic points, and constituting all linearity classifiers into cascade classifiers according to the linearity classifiers which are chosen by and corresponding to the series of characteristic points and the preset threshold. The invention fully utilizes the CNN characteristic redundancy, the multilayer characteristic calculation cost variation and multistage characteristic discrimination capability to realize the acceleration of the CNN on the binary classification and the specific object detection.

The invention discloses a network accelerating system. The network accelerating system comprises a VPN server and an accelerating server, wherein the VPN server extracts a network traffic data packagegenerated by a mobile terminal based on a data request and analyzes the extracted network traffic data package; the VPN server identifies a data type of the extracted network traffic data package according to an analysis result; the VPN server accelerates transmission of the network traffic data package through the accelerating server according to the identified data type or transmits the networktraffic data package as common data through an original path of the network traffic data. Corresponding network requests are identified and split according to the data type of the network traffic data package, the network bandwidth is accelerated, bandwidth acceleration cost is saved, and unnecessary resource loss is prevented.

The invention discloses a Winograd YOLOv2 target detection model method based on FPGA acceleration. The method comprises the steps: employing a PYNQ board card, and enabling a main control chip of thePYNQ board card to comprise a processing system end PS and a programmable logic end PL; wherein the PS end caches a YOLO model and feature map data of a to-be-detected image; the PL end caches the parameters of the YOLO model and the to-be-detected image into an on-chip RAM, deploys a YOLO accelerator with a Winograd algorithm, completes acceleration operation on the model, forms a data path of ahardware accelerator, and realizes target detection of the to-be-detected image; and an operation result of the acceleration circuit can be read out, and image preprocessing and display are carried out. By adopting the technical scheme of the invention, the calculation complexity of the YOLO algorithm can be reduced, the FPGA accelerator storage optimization algorithm reduces the calculation timeof the FPGA when accelerating the YOLO algorithm, accelerates the target detection, and effectively improves the performance of the target detection.

The invention discloses a PBKDF2 cryptographic algorithm accelerating device. The device comprises a CPU+FPGA (Field-Programmable Gate Array) heterogeneous system composed of an FPGA and a universal CPU. The invention further provides a PBKDF2 cryptographic algorithm accelerating method. The method comprises the following steps: 1) initial: computing a pre-computing part and a part before a loop body of a PBKDF2 algorithm is executed in a CPU, and transmitting a computed result to the FPGA via a bus interface; 2) loop: placing a computing-intensive loop body part in the PBKDF2 algorithm onto the FPGA, improving an acceleration effect and a resource utilization efficiency on the FPGA using an optimization means, and transmitting the computed result to the CPU via the bus interface; and 3) check: reading result data obtained after FPGA accelerated computing, and performing computed result summarization as well as check value computation and judgment.

The invention provides an application program acceleration method and device, electronic equipment and a storage medium, relates to the technical field of computers. The application program acceleration method comprises the steps of when it is detected that an intelligent acceleration service is in a starting state, monitoring whether a target object starts a current application program at a foreground or not; in response to the fact that the target object starts the current application program at the foreground, judging whether the number of historical application programs in a preset dynamicacceleration list is greater than or equal to a preset threshold value or not; if it is judged that the number of the historical application programs in the preset dynamic acceleration list is largerthan or equal to a preset threshold value, deleting the historical application program started firstly in the preset dynamic acceleration list so as to add the current application program into the preset dynamic acceleration list; and performing network acceleration on the historical application programs and the current application programs in the preset dynamic acceleration list in a preset network acceleration mode. According to the invention, the network speed of the application programs in the acceleration list can be ensured, and the user experience is improved.

The invention discloses a compression and acceleration method based on a deep neural network model. The compression and acceleration method comprises the following steps: 1) initializing a pre-trainedconvolutional network; 2) applying a global mask to all the filters, wherein the global mask is equal to 1; and 3) iteratively adjusting the sparse network and updating the filter significance. According to the compression and acceleration method based on the deep neural network model, the accuracy loss of the neural network is reduced through the pruned neural network, and the calculated amountand the scale of the neural network model can be compressed by multiple times on the premise that the algorithm precision of the neural network is not lost basically.

The invention discloses a network acceleration method and system, belonging to the technical field of networks. The method includes the following steps that: user equipment sends a query accelerationrequest including a target access address to a query server; the query server receives the query acceleration request, determines an acceleration router address corresponding to the target access address included in the query acceleration request, and returns the acceleration router address to the user equipment; and the user equipment receives the acceleration router address, sends an access request of the target access address to the corresponding acceleration router according to the acceleration router address, and receives an access response returned by the acceleration router. According to the scheme of the invention, the network acceleration is realized by querying the query server for the acceleration router address and accessing a corresponding service server through the acceleration router corresponding to the query server, the operation of adding an acceleration server in each area corresponding to each service server is not required, and thus the network structure can be simplified, the cost of network deployment can be reduced, and the user experience can be further improved.

The embodiment of the invention provides a multi-network access method and terminal equipment, relates to the technical field of communication, and aims to solve the problem that the data transmissionspeed of interaction between the existing terminal equipment and a network cannot meet the use requirements of users. The method comprises the following steps: receiving a first input of a user to anetwork acceleration identifier, wherein the network acceleration identifier is an entrance for triggering terminal equipment to access a network; in response to the first input, displaying a target interface, wherein the target interface comprises at least one of a first control and a second control, the first control is used for triggering the terminal device to access M second wireless local area networks under the condition of accessing the first wireless local area network, the second control is used for triggering the terminal equipment to access N mobile data networks under the condition of accessing the first wireless local area network, and the speed of transmitting the data based on the plurality of accessed networks is greater than the speed of transmitting the data based on thefirst wireless local area network. The method can be applied to a network acceleration scene of the terminal equipment.

Embodiments of the invention disclose an application acceleration method and apparatus. The method is implemented by comprising the steps that a control center calls a process monitoring class to monitor start and stop of a process; the control center receives process information; the process information is sent to the control center after the process monitoring class monitors that a process is started and the process is a process to be accelerated; and the control center calls a business class, enables the business class to monitor state change of the process, and executes a corresponding task in a current state of the process until the states of all processes are stop states. In the whole acceleration process, an application can be accelerated only when configuration data in the business class can support process acceleration, and tasks in a process execution process can be multiplexed/shared by different processes without code modification, so that the operation and maintenance efficiency can be improved by the acceleration scheme adopted by the method and the apparatus.

The invention discloses a cache acceleration management method for volumes in a storage. The method comprises the steps of selecting a cache partition; acquiring data information of the cache partition, wherein the data information comprises a mode of the cache partition, a node ID of the cache partition and an IO group ID of the cache partition; traversing all the volumes in the storage, and determining a node ID of each volume and an IO group ID of each volume; according to the data information, the node ID of each volume and the IO group ID of each volume, determining a volume set serving as an acceleration object of the cache partition from all the traversed volumes; and sending acceleration starting instructions to any number of the volumes in the volume set so as to achieve cache acceleration of the volumes receiving the acceleration starting instructions. By applying the method, all the volumes, capable of being subjected to cache acceleration management, of the cache partitionare determined, so that the management efficiency of batch cache acceleration of the volumes is improved. The invention further discloses a cache acceleration management system and device for the volumes in the storage, and a storage medium, which have the corresponding technical effects.

The invention provides an ultrahigh-definition video image analysis acceleration method and an ultrahigh-definition video image analysis acceleration system based on the ultrahigh-definition video image analysis acceleration method. The method is used for carrying out real-time processing and analysis on ultrahigh-resolution video images by adopting an analysis platform comprising a plurality of image calculation units, and is characterized by comprising the following steps: S1, establishing a data transmission channel for acquiring the video images, continuously acquiring image frames of thevideo images, and directly storing the image frames; S2, sequentially setting sequence marks for the acquired image frames according to the acquisition sequence; S3, analyzing the calculation performance of the image calculation units, further determining the processing sequence of each image calculation unit, and generating a corresponding processing scheme; S4, controlling a corresponding imagecalculation unit to carry out image analysis calculation on the image frame according to the processing scheme so as to obtain an analysis result; And S5, sequentially storing the corresponding analysis results according to the sequence marks.

The invention relates to a width-first search algorithm-oriented acceleration device and method and a storage medium. The device comprises a memory module which is used for storing graph data and a search result, a execution unit module which is used for constructing a multi-stage assembly line according to the internal characteristics of the width-first-oriented search algorithm so as to executea traversal search task, a memory access multiplexing module which is used for processing a memory access request of the assembly line according to a set priority, a scheduling module which is used for distributing the response data of the memory module to an idle execution unit; and a control module which is used for controlling and managing each module. The method and the device can improve thecomputational efficiency of graph data processing.

The invention provides an Ethernet application layer protocol control system based on hardware acceleration. An FPGA performs protocol analysis on application layer network protocol packets, matches the analysis result by utilizing a plurality of parallel protocol identification algorithms, executes a corresponding control operation according to the matching result, discards or forwards the application layer network protocol packets which do not need to be subjected to deep processing, and transmitting the application layer network protocol packets which need to be subjected to deep processingto a CPU for processing; and the FPGA receives and forwards a processing result returned by the CPU to realize protocol control of the application layer. According to the system, a software and hardware combination mode is adopted, the communication connection between the FPGA and the CPU is added, a process of analyzing and processing application layer network protocol packets in a CPU in the prior art is transferred to an FPGA to be realized, the application layer network protocol packets are processed in parallel through the FPGA, and the application layer network protocol packets needingto be processed by the CPU are captured and intercepted and are transmitted back to the CPU for processing, so that the burden of the CPU is greatly reduced, the Ethernet application layer protocol control efficiency is improved, and CPU acceleration is realized.

The invention provides a sparse convolutional neural network acceleration method and system based on a data flow architecture. For sparse convolution application, a set of instruction sharing detection device and a sparse convolution acceleration method are designed in a software mode. The instructions generated by the compiler are detected and compared, the instructions with the completely same instruction content in all the instructions are marked, the addresses of the instructions are set to be the same addresses, instruction sharing in sparse convolution is achieved, therefore, access of instruction loading to a memory is reduced, and the sparse convolution running time is prolonged.

The invention provides a processing method and a processing device for a page content, a main node and an auxiliary node, wherein the processing method comprises the steps of acquiring the page content of a hyper text transfer protocol (HTTP) page in a forward broadcast system by a main node of the forward broadcast system; and transmitting the page content to an auxiliary node of the forward broadcast system by the main node in a multicast or broadcast manner, wherein the auxiliary node is used for performing feedback of the page content which corresponds with the HTTP request to a user terminal through triggering of the HTTP request which is transmitted from the user terminal. The processing method, the processing device, the main node and the auxiliary node has advantages of settling aproblem of incapability of effectively adapting a limited-bandwidth system by HTTP page accelerating technology in related technology, furthermore saving bandwidth flow, and realizing user HTTP accessing acceleration on the condition that the occupied bandwidth is reduced.

The invention provides an acceleration method and device based on ATE equipment chip testing and a testing machine system. The acceleration method comprises the following steps: selecting and configuring a pin circuit chip; the pin circuit chip collects test data fed back by the chip to be tested; at a preset time interval, the FPGA on each service board reads the test data in all the pin circuit chips on the service board in parallel, and stores the read test data in the FPGA; the test program obtains test data of all pin circuit chips on the service board by reading data stored in the FPGA on each service board; and the test program analyzes the test data to complete the test of the to-be-tested chip. According to the scheme provided by the invention, by reducing the access times of the test program to the pin circuit chip in the chip test process of the ATE equipment, the configuration time and reading time of the chip are reduced, the chip test time is shortened, the chip test efficiency is improved, hardware adjustment is not needed, and only the FPGA on the service board needs to be designed and upgraded.

The invention discloses an electromagnetic power thruster which comprises an ionization section, an accelerating section and a neutralization jet section. The thruster is characterized in that the ionization section is composed of a graphite electrode pipeline (2) which is connected with a tail gas jet port end of a micro rocket engine (1); the accelerating section comprises a weak electrode pipeline (4) and an enhancement electrode plate (9) on the outer periphery of the weak electrode pipeline (4), and the weak electrode pipeline (4) penetrates through an annular channel formed by an outer cylindrical magnet (5) and an inner cylindrical magnet (6); the neutralization jet section comprises a cathode ray pipe (8) installed on the outer side of the weak electrode pipeline (4) , a front magnetism-isolating sleeve (3) is arranged between the ionization section and the accelerating section, and a rear magnetism-isolating sleeve (7) is arranged between the accelerating section and the neutralization jet section. The electromagnetic power thruster is simple in structure and low in manufacturing cost, energy is saved, the specific impulse and the thrust-to-power ratio can be adjusted at will according to requirements, the single equipment can bear high power, and large thrust force can also be obtained.