Intelligent acceleration chip suitable for power system edge calculation

Abstract

The invention discloses an intelligent acceleration chip suitable for edge computing of a power system. The intelligent acceleration chip comprises an AXI4.0 bidirectional bus, a DDR SDRAM acceleration module, an embedded microcontroller and an AXI4.0 bidirectional bus, and the DDR SDRAM is used for storing the lightweight neural network model, and the acceleration module is connected with the AXI4.0 bidirectional bus and the DDR SDRAM and is used for executing convolution, nonlinearity and pooling operation according to the lightweight neural network model, wherein the embedded microcontroller is connected with the AXI4.0 bidirectional bus, and the embedded microcontroller carries out command interaction with the acceleration module through the AXI4.0 bidirectional bus so as to control the operation of the acceleration module. The intelligent acceleration chip suitable for edge calculation of the power system realizes chip-level acceleration of convolution operation, nonlinear operation and pooling operation, and is simple in structure, low in power consumption and high in operation speed.

Description

technical field [0001] The invention relates to the field of power edge computing, in particular to an intelligent acceleration chip suitable for power system edge computing. Background technique [0002] With the continuous and in-depth development of smart grids, edge computing, which is a combination of artificial intelligence and the Internet of Things, plays an important role in the power system. How to complete the artificial intelligence deep neural network reasoning process on the edge side power terminal is a problem that power technicians have been perplexing. The problem. Due to the large amount of calculation of the artificial intelligence model and the high real-time requirements of edge computing, it is urgent to accelerate the deep neural network model running on the terminal. Currently, there are two main methods, one is to compress the network model, and the other is to design a special intelligent acceleration chip. [0003] Due to the popularity of deep ...

AI Technical Summary

Problems solved by technology

[0005] The implementation of intelligent systems on edge devices must withstand the challenges of cost, accuracy and calculation speed. Due to the large amount of calculation of the neural network, it is still difficult to meet the real-time requirements. In addition, the battery power supply also requires high power consumption. The cost of coming to the terminal is greatly increased

Neural network calculation is mainly convolution calculation, common ones include im2col, Winograd, systolic array, FFT fast Fourier transform, etc., but implementing these operations at the embedded low-power chip level is not conducive to the deployment of edge computing battery-powered terminals

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