Ethernet application layer protocol control system and method based on hardware acceleration

An application layer protocol and hardware acceleration technology, which is applied in the computer field, can solve problems such as system instability, failure to recover, and attacks, and achieve the effects of CPU acceleration, reducing the burden on the CPU, and improving efficiency

Active Publication Date: 2020-06-05
深圳市龙信信息技术有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This processing method not only has very low processing efficiency, but also brings a huge operating burden to the CPU. The long-term high-load operation of the CPU will also lead to system instability, a

Method used

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  • Ethernet application layer protocol control system and method based on hardware acceleration
  • Ethernet application layer protocol control system and method based on hardware acceleration
  • Ethernet application layer protocol control system and method based on hardware acceleration

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0021] A kind of Ethernet application layer protocol control system based on hardware acceleration, see figure 1 ,

[0022] Including an FPGA electrically connected to the CPU;

[0023] Described FPGA is provided with a plurality of processing engines, realizes the parallel processing of application layer network protocol packet; Described FPGA is used for receiving application layer network protocol packet, carries out protocol analysis to described application layer network protocol packet, and utilizes multiple parallel The protocol identification algorithm matches the analysis results, and performs corresponding control operations according to the matching results; the control operations include discarding or forwarding application-layer network protocol packets that do not require in-depth processing, and application-layer network protocol packets that will require in-depth processing transmitted to the CPU for processing;

[0024] The FPGA is also used to receive the p...

Embodiment 2

[0049] A kind of Ethernet application layer protocol control method based on hardware acceleration, see figure 2 , including the following steps:

[0050] S1: FPGA receives the application layer network protocol packet, and performs protocol analysis on the application layer network protocol packet;

[0051] S2: The FPGA uses a variety of parallel protocol recognition algorithms to match the analysis results, and performs corresponding control operations according to the matching results; the control operations include discarding or forwarding application layer network protocol packets that do not require in-depth processing, and performing The deeply processed application layer network protocol packet is transmitted to the CPU for processing;

[0052] S3: The FPGA receives the processing result returned by the CPU after processing the application layer network protocol packet, forwards the processing result, and realizes the protocol control of the application layer.

[00...

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PUM

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Abstract

The invention provides an Ethernet application layer protocol control system based on hardware acceleration. An FPGA performs protocol analysis on application layer network protocol packets, matches the analysis result by utilizing a plurality of parallel protocol identification algorithms, executes a corresponding control operation according to the matching result, discards or forwards the application layer network protocol packets which do not need to be subjected to deep processing, and transmitting the application layer network protocol packets which need to be subjected to deep processingto a CPU for processing; and the FPGA receives and forwards a processing result returned by the CPU to realize protocol control of the application layer. According to the system, a software and hardware combination mode is adopted, the communication connection between the FPGA and the CPU is added, a process of analyzing and processing application layer network protocol packets in a CPU in the prior art is transferred to an FPGA to be realized, the application layer network protocol packets are processed in parallel through the FPGA, and the application layer network protocol packets needingto be processed by the CPU are captured and intercepted and are transmitted back to the CPU for processing, so that the burden of the CPU is greatly reduced, the Ethernet application layer protocol control efficiency is improved, and CPU acceleration is realized.

Description

technical field [0001] The invention belongs to the technical field of computers, and in particular relates to an Ethernet application layer protocol control system and method based on hardware acceleration. Background technique [0002] The data processing performed by the traditional CPU on the received application layer network protocol packets includes protocol packet analysis, control operations, etc. Among them, the analysis of the protocol packet, the control operation and other processing are all operated by the CPU, and the CPU can only process the protocol packet one by one in the way of serial identification and serial control. This processing method not only has very low processing efficiency, but also brings a huge operating burden to the CPU. The long-term high-load operation of the CPU will also lead to system instability, and it is also easy to be attacked; once the CPU fails, it will It directly leads to system crash and data damage, so there are problems o...

Claims

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Application Information

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IPC IPC(8): H04L29/06H04L29/08
CPCH04L69/22H04L69/329
Inventor 王斌
Owner 深圳市龙信信息技术有限公司
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