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Code Cache management method in dynamic binary translation

A technology of dynamic binary and management methods, applied in the field of dynamic binary translation, can solve problems such as complex implementation and increase runtime overhead, and achieve the effects of low system extra overhead, avoidance of repeated translation, and low management overhead.

Active Publication Date: 2013-06-12
ZHEJIANG UNIV
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  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

The disadvantages are: 1) An additional ordered linked list is required to manage code blocks, which is complicated to implement and increases runtime overhead; 2) In order to generate enough space to store newly generated code blocks, code that does not conform to the LRU principle The block is replaced; 3) Cache memory fragmentation will be generated
[0014] The code cache management strategy plays an important role in improving translation efficiency in dynamic binary translation. It needs to comprehensively consider issues such as management overhead, code locality, and code fragmentation. However, existing code cache management strategies still have various deficiencies. Therefore, It is urgent to propose a more effective code cache management strategy

Method used

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  • Code Cache management method in dynamic binary translation
  • Code Cache management method in dynamic binary translation
  • Code Cache management method in dynamic binary translation

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Embodiment 1

[0045] The dynamic binary translation system used in this embodiment is an open source QEMU system, but this method can also be extended to other binary translation systems. The QEMU system translates the executable file of the source target architecture (such as ARM, X86, MIPS) into intermediate code, and then translates it into the target architecture ISA (Instruction Set Architecture) (such as X86, PowerPC, ARM, Sparc, Alpha, MIPS ) on execution. The unit of translation is the basic block, which is a sequence of instructions that ends with a jump instruction or an instruction that changes the state of the processor. QEMU uses TCG as the intermediate code. Each source architecture instruction will be translated into one or more TCG instructions at the front end, and these TCG instructions will be translated into target architecture code at the back end. TCG has a simple, clear grammatical structure.

[0046] QEMU's dynamic binary translation process is as follows figure 1...

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Abstract

The invention relates to a dynamic binary translation technology in the field of computer application, and discloses a code Cache management method in the dynamic binary translation. The code Cache comprises a non-skip target Cache and a skip target Cache, and adopts an FIFO (first in and first out) strategy. The method comprises the following steps: determining types of translation basic blocks; executing a non-skip target basic block processing procedure when the basic blocks are non-skip target basic blocks; and executing a skip target basic block processing procedure when the basic blocks are skip target basic blocks. The code Cache management method in the dynamic binary translation has the advantages that translated codes can be cached effectively, and the repeated translation is reduced.

Description

technical field [0001] The invention relates to the dynamic binary translation technology in the computer application field, in particular to a code Cache management method in the dynamic binary translation. Background technique [0002] Dynamic binary translation technology is an effective means to solve legacy code and improve software platform adaptability. It dynamically converts binary programs on the source architecture to run on other target architectures without the need for executable program source code. Dynamic binary translation basically works like this: translate the source architecture binary code in units of basic blocks, generate corresponding code blocks supported by the target architecture through translation, and cache them in the code cache, so that when the program runs to this basic block again When the block is executed, the corresponding target architecture code is directly obtained from the code cache and executed, thereby improving the execution s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/45G06F12/08G06F12/1027
Inventor 李莹罗艳尹建伟吴健邓水光吴朝晖
Owner ZHEJIANG UNIV
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