10 results about "Just-in-time compilation" patented technology

The invention is suitable for the technical field of computers, and provides a CPU and GPU cooperative work heterogeneous computing method and platform, and the method comprises the following steps: S1, carrying out the meta-task analysis of an input computing task, extracting the computing feature metadata of the computing task, and predicting the performance of the computing task based on a pre-trained performance prediction model; dynamically deciding execution path planning of the task between the CPU and the GPU; s2, according to the execution path planning, carrying out adaptive resource collaborative configuration; and S3, on the basis of the calculation feature metadata and the current hardware state, through a parameterized kernel template or a just-in-time compilation technology, heterogeneous perception optimized kernel codes are generated. The method effectively solves the problems that a task scheduling strategy is rigid, the bottleneck of memory and data transmission is prominent, calculation kernel optimization is insufficient and is lack of adaptability, and a system is lack of self-evolution and learning ability.

The invention discloses a real-time compiling interpreter system capable of running on an MCU (Microprogrammed Control Unit), an FPGA (Field Programmable Gate Array), a GPU (Graphics Processing Unit) or a universal CPU (Central Processing Unit), and belongs to the technical field of embedded systems and computer compiling. According to the system, hardware decoupling is achieved through a modular architecture, and C / C + +, Python and LLVM intermediate codes are supported to be converted into unified intermediate byte codes; a byte code interpreter and an instant compiling module are integrated, both quick starting and efficient execution are considered, and starting can be completed within 1 millisecond; an event driving and periodic scheduling mechanism is provided, and the real-time response requirement is met; a segmented memory model and a security policy are adopted, low-power-consumption edge equipment is adapted, and domestic instruction sets such as RISC-V and LoongArch are compatible. The system solves the problems that a traditional embedded system is poor in flexibility, difficult in cross-platform, insufficient in real-time performance and the like, can achieve unified execution of heterogeneous platform codes, is suitable for the fields of industrial control, Internet of Things edge AI and the like, and has remarkable technical progress and industrial value.

The application relates to a standard system for decoupling a training framework and an instant compiler and a working method thereof, the system comprising a standard interface layer for connecting the training framework and the instant compiling component, wherein a compiling standard interface and an executor standard interface are arranged in the standard interface layer; the method comprises the following steps: based on the compiling standard interface, developing a neural network executor, a neural network compiler, a compiling task data structure, a compiling error output data format and a compiling correct output data format respectively; registering a unique identifier of the neural network compiler to the training framework, and accessing the neural network compiler by the training framework through calling the compiling standard interface; and returning an execution result to the training framework by the neural network executor. Compared with the prior art, the application can enable the training framework to access the neural network compiler of different chip manufacturers through one-time adaptation, thereby effectively reducing the adaptation cost between the training framework and the neural network compiler and realizing the rapid access of the training framework and the compiling component.

This invention discloses a method for accelerating numerical computation software based on CPU-GPU collaboration. The method divides the program into basic blocks and uses a code analysis module to predict the runtime information of these basic blocks, including whether they are computationally intensive tasks, whether they are easily parallelized, and whether the memory copy time of the computation task is less than the CPU execution time. Based on the analysis results, basic blocks that meet the above conditions are marked as GPU modules, and the rest are CPU modules. GPU modules are compiled into GPU code for execution on the fly. If CPU modules have hotspot code, they are compiled into machine code on the fly for execution; otherwise, they are interpreted. This method employs a CPU-GPU collaborative just-in-time compilation approach, fully utilizing CPU and GPU computing resources, achieving higher execution efficiency than CPU or GPU execution alone. It also leverages the advantages of just-in-time compilation of interpreted languages, significantly improving the performance of numerical computation software.

The application relates to the field of data processing and communication technology, and discloses a standardized implementation method of a dynamic automatic translation device, which comprises the following steps: constructing and analyzing a standard configuration model, generating an attribute dependency matrix, performing loop detection and topological sorting, generating a linear ordered execution sequence, presetting a class code skeleton and a runtime context, extracting a logic code set according to the sequence, applying a code synthesis equation to generate a composite logic source code, calling an instant compiler and an isolated class loader to convert the source code into a dynamic translation instance and perform atomic reference replacement, and feeding device original data into the instance to make the device original data flow in a logical path in a one-way manner in the runtime context to complete translation. Through the conversion of the interpretive execution into the compiled sequential execution, the application eliminates runtime dependency lookup, cooperates with the isolated loading and atomic replacement mechanism, realizes the independent running and smooth hot updating of the device logic, and improves the efficiency and stability of the heterogeneous protocol adaptation.

This invention proposes a hardware-assisted isolated execution method for eBPF programs, comprising: acquiring the eBPF program to be executed; setting all data pages accessed in the eBPF program to non-privileged pages; issuing all memory access instructions in the eBPF program as non-privileged access instructions through just-in-time (JIT) compilation to obtain the program to be executed; running the program to be executed in kernel mode EL1 of the server operating system to obtain the execution result; and during the execution of the program to be executed, the non-memory access instructions in the program to be executed run at the kernel mode EL1 privilege level, and the memory access instructions in the program to be executed are non-privileged access instructions, which are run at the user mode EL0 non-privileged level. By setting the memory of the eBPF program to non-privileged pages, the eBPF program still runs at a privileged level, but is issued with non-privileged memory access instructions. Since the kernel memory is set to privileged pages, the eBPF program cannot access them, thereby ensuring kernel memory safety.

Dynamic trace sizing for tracing just-in-time compilation is provided. A trace of a program is generated during a tracing phase of the just-in-time compilation. The trace of the program is profiled to determine an estimated effective trace size prior to compiling the trace. Additional profiling is performed to determine a garbage collection time and consequently a total execution time of the program based on the estimated effective trace size determined prior to compiling the trace. It is determined whether to continue formation of the trace or trigger termination of the trace based on the garbage collection time of the program. Triggering the termination of the trace dynamically sizes the trace at runtime of the program.

This invention relates to database query execution optimization. Specifically, it describes techniques for optimal execution based on query interpretation translated into a domain-specific language (DSL) using optimizations such as partial evaluation, abstract syntax tree (AST) rewriting, just-in-time (JIT) compilation, dynamic analysis, speculative logic, and Futamura projection. In an embodiment, a database management system (DBMS) hosted on a computer generates a query tree representing a database query, which contains expressions represented by subtrees of the query tree. The DBMS generates a sequence of DSL instructions representing the subtrees. During the execution of the database query, the sequence of DSL instructions is executed to evaluate the expressions. In an embodiment, the AST is generated from the sequence of DSL instructions. In an embodiment, the DSL AST is optimally rewritten based on a runtime feedback loop that includes dynamic profiling information.

A RISC-V emulator format output function implementation method, device and equipment and storage medium are disclosed, and belong to the technical field of emulators. The method comprises the following steps: obtaining a RISC-V source code to be simulated, inputting the RISC-V source code to be simulated into a compiler, and obtaining a first code file translated by the compiler; in the case that a format string of a first printf function includes a string placeholder %s, translating the first code file into a second code file comprises translating the first printf function into an IR form based on a first jump table and a second jump table corresponding to %s in the format string of the first printf function; after the first code file is translated into the second code file, the second code file is executed by using a just-in-time compiler. The method can accurately and effectively implement the printf function in the RISC-V emulator.

The application is suitable for the technical field of computers, and provides a heterogeneous computing method and platform for CPU and GPU to work cooperatively, wherein the method comprises the following steps: step S1: performing meta-task analysis on an input computing task, extracting computing feature metadata thereof, and dynamically deciding execution path planning of the task between CPU and GPU based on a pre-trained performance prediction model; step S2: performing adaptive resource cooperative configuration according to the execution path planning; and step S3: generating heterogeneous-aware optimized kernel code based on the computing feature metadata and a current hardware state through a parameterized kernel template or a just-in-time compilation technology. The application effectively solves the problems of rigid task scheduling strategy, prominent memory and data transmission bottlenecks, insufficient and lack of adaptability of computing kernel optimization, and lack of self-evolution and learning ability of the system.