48 results about "Analog circuit design" patented technology

The invention discloses a single-pin trimming circuit, which relates to the technical field of analog circuit design and comprises a comparator module, a first input end of the comparator module is connected to a single pin, a second input end of the comparator module is connected to a reference voltage, and the comparator module is used for comparing an input voltage of the single pin with the reference voltage and outputting a comparison signal; the input end of the time sequence decoding module is connected to the output end of the comparator module, and the time sequence decoding module is configured as follows: a, the logic state of a trimming position is judged according to the duration time of the pulse in the comparison signal; and b, addressing different trimming positions according to the number of pulses in the comparison signal, and further generating a multi-position trimming control signal through a series of pulse signals input by the single pin. Accurate control of a multi-bit fuse trimming circuit in a chip is realized by using single-pin resources.

An example is a non-transitory computer-readable storage medium including stored instructions. The instructions, which when executed by one or more processors, cause the one or more processors to: obtain an assignment of an assigned bucket; generate stimulus values targeting one or more uncovered bins of the assigned bucket; simulate operation of a circuit design using the stimulus values; determine whether the assigned bucket has been covered by the simulated operation of the circuit design; and expand a size of the assigned bucket following a determination that the assigned bucket has been covered. The assigned bucket, as assigned, has a subset of bins of a functional coverage space.

The embodiment of the invention provides a method, device and equipment for simulating circuit layout design, a medium and a program product, and relates to the field of chip design tools. The method includes determining layout design constraints associated with a plurality of device groups in a circuit design based on circuit design data, and generating a plurality of layout cell groups based on the layout design constraints, each layout cell group having an internal layout and an internal connection. The method further includes generating a layout by modifying at least one of a position and a shape of the plurality of layout cell groups based on the layout design constraints, determining a global layout of the plurality of layout cell groups, and determining wiring based on the layout design constraints. In this way, the layout design constraint can be automatically determined from the analog circuit design data, and then the layout unit group, layout and wiring are automatically generated in combination with the layout design constraint, so that end-to-end automatic generation of the analog circuit layout is realized.

The present invention proposes an analog circuit intelligent design method based on process and post-simulation optimization feedback, which belongs to the field of multi-objective optimization of circuit design. The method includes three processes: a circuit diagram optimization process, a layout optimization process, and a device process optimization process. The circuit diagram optimization process uses the GLAL-MOPSO algorithm to optimize the parameters of circuit components; the layout optimization process designs a strategy for grouping decision variables on the basis of the GLAL-MOPSO algorithm to cope with the optimization problem of large-scale variables in layout optimization; in order to increase the optimization range of circuit design, the device process optimization process is added to the circuit optimization process. The process optimization process uses the GLAL-MOPSO algorithm to optimize the parameters of the device process, and the results obtained in the device process optimization process can be used as the basis for re-optimization of the circuit diagram and layout. The present invention saves time cost and manual design cost by automating the optimization iteration of analog circuit design and device process optimization, and effectively improves the design efficiency of the circuit.

An analogue circuit design apparatus is configured to receive information representing electrical requirements for the analogue circuit, identify a plurality of potential layout techniques such as symmetrical, common centroid, and interdigitated layout technique, select one of the potential layout technique as the current selected layout technique, and determine physical properties of the analogue circuit based on the electrical requirements and the current selected layout technique. The analogue circuit design apparatus is configured to determine whether the current selected layout technique and determined physical properties of the analogue circuits meet the electrical requirements, and in the event that they do meet the electrical requirements, produce and output a design, or if they do not meet the electrical requirements, to repeat the process with a different selected layout technique as the current selected layout technique.

The invention discloses a low-frequency interference magnetic field elimination method and system, and belongs to the technical field of electromagnetism and control. The device mainly comprises a magnetic sensor module used for collecting interference magnetic field signals, a conversion circuit module used for converting the interference magnetic field signals into analog voltage signals, a characteristic frequency band interference signal selection module, an analog signal phase adjustment module, a multi-path characteristic frequency band interference signal addition module, an output gain adjustable module and a power amplification module. A magnetic field generation module and an elimination effect detection feedback module. According to the low-frequency interference magnetic field elimination system, an analog circuit design method is adopted, low-frequency interference magnetic fields of several different frequency bands can be effectively weakened and eliminated, and the low-frequency interference resistance of devices with high low-frequency interference sensitivity such as ultralow-field magnetic resonance imaging equipment can be improved by adjusting system related parameters; and the equipment availability is enhanced.

A semiconductor structure including first finfet cells and second finfet cells. Each of the first finfet cells has an analog fin boundary according to analog circuit design rules, and each of the second finfet cells has a digital fin boundary according to digital circuit design rules. The semiconductor structure further includes first circuits formed with the first finfet cells, second circuits formed with the second finfet cells, and third circuits formed with one or more of the first finfet cells and one or more of the second finfet cells.

The utility model discloses a CT self-power-taking protection device, and belongs to the technical field of power relay protection. The device comprises a fault current detection loop, a CT power taking loop and a self-protection module. The fault current detection loop is composed of a phase current detection device, a zero-sequence current synthesis detection device and an over-current fuse device and is used for detecting an inter-phase and zero-sequence over-current fault, and the over-current fuse device is fused when the fault occurs; the CT power taking loop is provided with a rectifier bridge, a CT opening voltage storage capacitor, a high-voltage trigger conduction diode and an output loop, CT opening energy can be obtained through the voltage storage capacitor and the diode, and the output loop drives a trip coil to trip off a circuit breaker to cut off a fault loop; the self-protection module comprises an overvoltage protection loop and an overcurrent protection loop, is composed of a current-limiting resistor, and can clamp and discharge abnormal high voltage and overcurrent in the loop. The device adopts a full-analog circuit design, has the advantages of quick response, high reliability, strong interference resistance and the like, can quickly and accurately act in a complex electromagnetic environment, and effectively guarantees the safety of a power system.

The invention discloses an interactive design method and system for simulating layout planning. The interactive design method comprises the following steps: A, selecting the type and shape of a component from a component list; b, editing a creation mode of the component according to the type of the component; c, editing component attributes and / or parameters; d, judging whether the parameters of the component attributes are legal or not, and if yes, executing the step E; otherwise, returning to the step C; and E, creating a graph of the component. By adopting the method and the device, information splitting between a framework design stage and a Floor Plan stage in an existing analog circuit design can be eliminated, repeated work and serial processes are reduced, and the design efficiency and consistency are improved.

The application discloses a low-noise instrument amplification circuit and system adopting a cross-temperature separation structure, relates to the technical field of analog circuit design and weak signal detection, and specifically comprises a low-temperature front-end component, a room-temperature end component and a cross-temperature connection cable. The low-temperature front-end component comprises a first junction field effect transistor (JFET), a second JFET and a source coupling resistor; the room-temperature end component comprises a first JFET constant current network, a second JFET constant current network, a first drain-source bias network, a second drain-source bias network and an operational amplifier circuit. The drain and the source of the first JFET and the second JFET are electrically connected to the room-temperature end component through the cross-temperature connection cable, and a signal source is connected between the gate of the first JFET and the gate of the second JFET through a shielded differential twisted pair. The structure aims to reduce the equivalent input current noise in the signal readout with a very high impedance temperature ratio and reduce the low-temperature thermal load.

The application belongs to the technical field of power supply, and particularly relates to a power supply control method and system, electronic equipment and storage medium. The method comprises the following steps: acquiring setting data from a memory, an upper computer or a device panel as a setting value; collecting sampling data through a high-speed analog-to-digital converter, and performing high-speed digital signal processing by using a programmable logic chip, and then performing stable voltage, stable current and stable power control; acquiring control parameters corresponding to the load characteristics closest to the current setting value from the storage data as the initial data of starting up, or quickly searching for the corresponding output real-time tracking reference value and the intermediate state value of loop control; and through closed-loop control, the output reaches the setting value for different load characteristics. The application reduces the design difficulty of analog circuit, improves the response characteristics, and is convenient for realizing higher performance power supply control; meanwhile, the signal processing can be dynamically realized by adjusting the register parameters, which is convenient for automatic calibration and mass production.

A system and method for inserting test points during circuit design testing are presented. The method includes partitioning a circuit design into a plurality of blocks and determining a first potential defect and a second potential defect for the circuit design. The method also includes simulating the circuit design by injecting, into the circuit design, the first potential defect to produce a first set of outputs of the plurality of blocks and simulating the circuit design by injecting, into the circuit design, the second potential defect to produce a second set of outputs of the plurality of blocks. The method further includes determining a set of output nodes of the plurality of blocks and generating a test that, when executed, measures signals at the set of output nodes.

This invention discloses an integrated high-voltage, high-current power distribution circuit using an external PNP transistor, belonging to the field of analog circuit design. It includes a high-voltage LDO module, a current detector, a digital controller, a digital current converter, and an external PNP transistor. The output of the error amplifier is simultaneously connected to the gates of MOSFET PM1 and PM2. The drain of MOSFET PM2 is connected to the input of the current detector, which is connected to a rise-fall counter in the digital controller. The rise-fall counter is connected to a digital-to-analog converter in the digital current converter, which is connected to a transconductance amplifier. The output of the transconductance amplifier is connected to the gate of MOSFET NM1, and the drain of MOSFET NM1 is connected to the base of transistor Q1 in the external PNP transistor. This invention achieves an integrated power distribution scheme by connecting an external PNP transistor and an LDO chip in parallel, achieving optimal results in power distribution and board area optimization. It has a simple structure, low cost, and well meets current needs.

The invention discloses a method for generating circuit topology based on a transfer function, relates to the technical field of circuit design, and solves the technical problem that it is difficult to combine an artificial intelligence method in circuit design to improve the efficiency and reliability of analog circuit design. The method comprises the following steps: based on a graph theory, establishing a connected graph G under a given RLC circuit structure and element parameters; deriving the relationship between the transfer function and the impedance or admittance of the network nodes of the connected graph G based on the RLC circuit; searching and calculating a tree and a secondary tree required by the transfer function, and calculating to obtain a final expression of the transfer function; analyzing the order and the structure of the transfer function, and combining specification constraints and design specifications of circuit design to obtain a circuit design rule; and searching topology and parameters of the RLC circuit through genetic programming to obtain an optimal topological structure and an optimal element admittance value. According to the method, automatic search of genetic programming is guided by analyzing the hard constraint rule set, and the efficiency and reliability of circuit comprehensive design are remarkably improved.

This application relates to a method, apparatus, device, and medium for designing analog circuits based on neural networks. The method includes: acquiring a training dataset for analog circuit design; designing the activation function type corresponding to the analog circuit design based on the training dataset and circuit model indicators; identifying the number of neurons in the initial neural network, and determining the processing mode and spatial distribution of the neuron circuit modules on the training dataset based on the number of neurons; designing the analog circuit according to the activation function type and the determined processing mode and spatial distribution to construct a neural network training circuit with a multi-level complex neuron group; and training the multi-level complex neuron group neural network training circuit using the training dataset to obtain a simulation-verified neural network circuit model. The entire scheme can achieve efficient and accurate analog circuit design.

This application discloses a computing system to simulate a circuit design describing an electronic device with a plurality of functional verification tests, separately collect samples of performance data during simulation of the circuit design for each of the functional verification tests, and generate test databases for each of the functional verification tests. Each of the test databases include samples for a corresponding functional verification test. The computing system can merge the samples of performance data in the test databases for the functional verification tests. The computing system can filter the merged samples of performance data into a subset of the merged samples of performance data based, at least in part, on profile filtering commands, and generate a profile presentation including the subset of the merged samples of performance data. The profile presentation, when displayed, can annunciate portions of the circuit design corresponding to at least one performance hotspot.

The invention belongs to the field of radio frequency integrated circuits, and particularly provides a frequency self-adaptive variable capacitance circuit of a microwave radio frequency band and application of the frequency self-adaptive variable capacitance circuit so as to meet the broadband design requirement of a radio frequency circuit. The invention provides an on-chip integrated frequency self-adaptive variable capacitance circuit which is completely based on microwave and analog circuit design and can be directly applied to various modules to realize self-adaptive change of capacitance along with frequency, so that the bandwidth of various modules is expanded; any other extra consumption except for the loss caused by the change of the capacitance Q value is not caused; meanwhile, the frequency self-adaptive variable capacitance circuit is applied to an output matching network of the radio frequency power amplifier, so that the broadband design of the radio frequency power amplifier is realized.

The application discloses a kind of non-functional device identification method in analog circuit design diagram, according to the netlist file of analog circuit, the component information and node information of analog circuit are extracted, traverse component dictionary set, short-circuit device is judged according to node information, then root node is selected, node tree is generated based on each root node respectively, Tarjan algorithm is used to identify cut point in analog circuit, according to cut point and make it become the subnode of cut point, carry out path search, the component on the path is used as non-functional component, short-circuit device and non-functional component are collected, and the final non-functional component set is obtained.The application can automatically identify non-functional component in analog circuit according to analog circuit diagram, reduce the fault number that analog circuit needs simulation, so as to shorten the time of analog circuit fault simulation.

This invention provides methods, systems, and programs that enable efficient circuit design. [Solution] An analog circuit design method using a large-scale language model, comprising the steps of: the large-scale language model receiving natural language input including information related to circuit specifications; the large-scale language model selecting knowledge information based at least on the input; the large-scale language model generating information necessary for circuit simulation based at least on at least a portion of the selected knowledge information; the circuit simulator executing a circuit simulation and generating information on the simulation results based at least on the necessary information; and the large-scale language model generating circuit design evaluation information based at least on at least a portion of the simulation results.

The invention relates to the technical field of analog circuit design, and discloses a ring amplifier, which is characterized by comprising a multi-stage amplification circuit and a level shift circuit, the input end of the multi-stage amplification circuit is connected with the signal input end of the ring amplifier, and the output end of the multi-stage amplification circuit is connected with the first end of the level shift circuit; the second end of the level shift circuit is connected with the signal output end of the ring amplifier; the level shift circuit comprises a first switch, a second switch, a third switch and a third capacitor, and the first end of the level shift circuit is connected to the second end of the level shift circuit through the first switch; the second end of the level shift circuit is connected with the first end of the third capacitor; the first end of the level shift circuit is connected with the second end of the third capacitor through the second switch. By arranging the multi-pole annular amplifying circuit and introducing the level shifting circuit, the index requirements of high gain, high bandwidth and low power consumption can be met under low voltage.

The present invention discloses a method for performing design space exploration, design optimization, and fine-tuning of analog circuits using a machine learning (ML) model. The method includes designing a base analog circuit, collecting SPICE simulation data for a random number of combinations of input, output, and process, voltage and temperature conditions, generating the data set from the simulation results, training the ML model using the generated dataset, identifying dominant circuit components in the base analog circuit configuration using Pearson correlation coefficients, generating from the trained machine learning model, a group of candidate analog circuit designs based on boundary conditions and desired specifications, and from the group of candidates calculating the candidate circuit that meets all the optimization criteria and the boundary conditions. The method further includes fine-tuning the optimized circuit by re-optimizing it for one or more specific sets of input, output, or PVT conditions to bring its specifications to the desired values.

A system and method generates test patterns for simulating a circuit design. Generating the test patterns includes determining clock data of the circuit design. The clock data is determined by determining a first clock signal pair from clock signals, and determining a disturb cell based on the first clock signal pair. The disturb cell is electrically coupled to a first clock signal of the first clock signal pair, and to a second cell. The second cell is electrically coupled to a second clock signal of the first clock signal pair, and an input of the second cell is electrically coupled to an output of the disturb cell. A first test pattern is generated based on the clock data and is output to a memory to be used in simulating a circuit design.

The invention provides an electron beam scanning positioning method and device, equipment and a storage medium. The scanning and positioning method of the electron beam comprises the following steps: acquiring scanning and positioning data of the electron beam in real time; based on a digital circuit, performing correction calculation on the scanning positioning data to obtain corrected scanning positioning data; determining an analog signal corresponding to the correction scanning positioning data; scanning positioning control of the electron beam is completed according to the analog signal. Visibly, through the method, the corrected scanning positioning data after correction can be quickly obtained through the correction operation based on the digital circuit, and compared with a scheme for correcting the scanning positioning signal by adopting an analog circuit, complex analog circuit design is not needed any more, the environmental noise influence caused by the complex analog circuit design is reduced, and the accuracy of scanning positioning signal correction is improved. And the scanning positioning efficiency and accuracy of the electron beam are improved.

The invention belongs to the technical field of machining, and particularly relates to a method for accurately driving a target vibration mode of an ultrasonic broaching machine, which comprises the following steps of: S1, designing a band-pass filter, carrying out a frequency sweep test, determining an axial modal bandwidth and carrying out thermal drift compensation; s2, realizing a digital filter, and optimizing a transition zone by adopting a Kaiser Window (Kaiser Window); a filter coefficient is quantized into a 18-bit fixed-point number format, so that the calculation efficiency during hardware implementation is improved; the FPGA is used for accelerating the filter, and the FIR filter is designed and has a linear phase characteristic so as to ensure that the signal is not distorted due to the filtering process; a standby analog circuit design is designed to serve as a supplement of a digital filter, and more redundancy and stability are provided. The broach vibration mode can be accurately driven, the purity of axial vibration is remarkably improved, the radial vibration suppression ratio is increased, and the machining precision and stability of ultrasonic equipment are further improved.

The embodiment of the present invention provides a vacuum detection circuit, a vacuum gauge, and a vacuum detection method, belonging to the field of vacuum measurement technology. The vacuum detection circuit includes: a carrier generation module, a capacitance detection module, and an output processing module connected in sequence. The vacuum detection circuit provided by the embodiment of the present invention is provided with a carrier generation module, a capacitance detection module, and an output processing module connected in sequence. A capacitance bridge including an inner ring capacitance of a thin film capacitor is provided in the capacitance detection module. The carrier is used as the voltage input end of the capacitance bridge. A square wave with the same frequency as the carrier is used to control the switching circuit, and the switching circuit is connected to the two midpoint voltage signals of the capacitance bridge when the square wave changes direction. The output processing module processes the signal output by the switching circuit to obtain a DC voltage signal reflecting the vacuum degree. The circuit adopts an analog circuit design, which greatly reduces system noise and reduces system cost.

The utility model discloses a current source circuit, a chip and electronic equipment, and belongs to the field of analog circuit design. The current source circuit comprises a current mirror unit, and the current mirror unit comprises a first switching tube and a second switching tube which are connected in series between an input voltage node and a grounding node; the third switch tube and the fourth switch tube are connected in series between the input voltage node and the grounding node, the driving end of the third switch tube is electrically connected with the driving end of the first switch tube, and the driving end of the second switch tube is electrically connected with the driving end of the fourth switch tube; the resistive element is arranged on a current path between the first switching tube and the second switching tube; and / or a resistive element is arranged on a current path between the third switch tube and the fourth switch tube, the resistive element is arranged on the current path between the switch tubes in the current mirror unit, the amplitude of the noise current on the current path can be attenuated, the modulation effect of the noise current on the output current is reduced, and therefore the current output precision is improved.

Methods, systems, and devices for tuning a set of simulation parameters associated with a design verification environment are described that include: simulating a circuit design according to a set of simulation parameters; providing, to a machine learning network, an indication of functional coverage results associated with simulating the circuit design according to the set of simulation parameters; receiving an output in response to the machine learning network processing the functional coverage results; and simulating the circuit design based on a recommended set of simulation parameters, wherein simulating the circuit design based on the recommended set of simulation parameters includes generating a set of component signals associated with satisfying a target functional coverage statement. In some aspects, the output includes: the target functional coverage statement associated with the circuit design; and the recommended set of the simulation parameters.

The invention discloses a digitally implemented low-power-consumption high-reliability over-temperature protection circuit, which belongs to the field of analog circuit design and comprises a positive temperature coefficient voltage generator, a comparator and a logic circuit, one input end of the positive temperature coefficient voltage generator is connected with a clock signal; the other input end of the positive temperature coefficient voltage generator is connected with the output end of the logic circuit; the output end of the positive temperature coefficient voltage generator is connected with the positive input end of the comparator, and the output end of the comparator is connected with one input end of the logic circuit. A positive temperature coefficient voltage generator is used for generating a voltage signal in direct proportion to temperature; the comparator generates an over-temperature protection signal which is not latched by comparing the positive temperature coefficient voltage with the band-gap reference voltage; and the logic circuit is used for latching the over-temperature protection signal output by the comparator into the memory, and changing an over-temperature protection detection temperature point by returning the latch signal to the positive temperature voltage generator, so that an over-temperature protection hysteresis function is realized.

The present invention provides an active noise reduction method based on analog circuit design, including a background current analysis module, an analog sampling feedback control unit, a power amplification unit, G1, G2, a signal conditioning circuit, a G3 current booster and an analog active noise reduction method equivalent circuit. In the power supply excitation stage, the background current analysis module inversely calculates the primary busbar current of the CTX to be calibrated through the secondary signal of CT0. G1 receives the CTX detection signal and forms a compensation current control signal. The compensation current control signal is transmitted to G2. The output end of the G2 circuit is signal-connected to the G3 current booster. The output end of the G3 current booster releases the output current and forms a closed loop. Moreover, G1 and the CTX detection signal are respectively inside the analog sampling feedback control unit, and G2 and the G3 current booster are respectively inside the power amplification unit.

The invention discloses an I ST power-on self-test acceleration system and method for a vehicle-mounted chip and a storage medium. The method has the advantages that a mechanism that a Logi c BIST test can be carried out after power-on reset is released is utilized, meanwhile, the reset of the PLL is released, the PLL reads adjusted clock parameters from eFuse and can quickly enter a Lock clock stable state, the PLL carries out Logic BIST Pattern test at the same time, and due to the fact that the PLL is an analog circuit and is isolated from a digital circuit of the LBIST in design, the test result of the LBIST cannot be influenced. Through the improvement, the MBIST test can be quickly entered without the need of starting PLL clock parameter configuration to wait for clock locking after the LBIST Pattern test is finished, and the MBIST test is started after the maximum time of a PLL Lock is usually waited in the original mode of configuring the PLL with the Pattern. By means of the improvement mode, the intermediate waiting time of IST can be greatly shortened.