21 results about "Analog circuit design" patented technology

The invention discloses a single-pin trimming circuit, which relates to the technical field of analog circuit design and comprises a comparator module, a first input end of the comparator module is connected to a single pin, a second input end of the comparator module is connected to a reference voltage, and the comparator module is used for comparing an input voltage of the single pin with the reference voltage and outputting a comparison signal; the input end of the time sequence decoding module is connected to the output end of the comparator module, and the time sequence decoding module is configured as follows: a, the logic state of a trimming position is judged according to the duration time of the pulse in the comparison signal; and b, addressing different trimming positions according to the number of pulses in the comparison signal, and further generating a multi-position trimming control signal through a series of pulse signals input by the single pin. Accurate control of a multi-bit fuse trimming circuit in a chip is realized by using single-pin resources.

An analogue circuit design apparatus is configured to receive information representing electrical requirements for the analogue circuit, identify a plurality of potential layout techniques such as symmetrical, common centroid, and interdigitated layout technique, select one of the potential layout technique as the current selected layout technique, and determine physical properties of the analogue circuit based on the electrical requirements and the current selected layout technique. The analogue circuit design apparatus is configured to determine whether the current selected layout technique and determined physical properties of the analogue circuits meet the electrical requirements, and in the event that they do meet the electrical requirements, produce and output a design, or if they do not meet the electrical requirements, to repeat the process with a different selected layout technique as the current selected layout technique.

The utility model discloses a CT self-power-taking protection device, and belongs to the technical field of power relay protection. The device comprises a fault current detection loop, a CT power taking loop and a self-protection module. The fault current detection loop is composed of a phase current detection device, a zero-sequence current synthesis detection device and an over-current fuse device and is used for detecting an inter-phase and zero-sequence over-current fault, and the over-current fuse device is fused when the fault occurs; the CT power taking loop is provided with a rectifier bridge, a CT opening voltage storage capacitor, a high-voltage trigger conduction diode and an output loop, CT opening energy can be obtained through the voltage storage capacitor and the diode, and the output loop drives a trip coil to trip off a circuit breaker to cut off a fault loop; the self-protection module comprises an overvoltage protection loop and an overcurrent protection loop, is composed of a current-limiting resistor, and can clamp and discharge abnormal high voltage and overcurrent in the loop. The device adopts a full-analog circuit design, has the advantages of quick response, high reliability, strong interference resistance and the like, can quickly and accurately act in a complex electromagnetic environment, and effectively guarantees the safety of a power system.

The application discloses a low-noise instrument amplification circuit and system adopting a cross-temperature separation structure, relates to the technical field of analog circuit design and weak signal detection, and specifically comprises a low-temperature front-end component, a room-temperature end component and a cross-temperature connection cable. The low-temperature front-end component comprises a first junction field effect transistor (JFET), a second JFET and a source coupling resistor; the room-temperature end component comprises a first JFET constant current network, a second JFET constant current network, a first drain-source bias network, a second drain-source bias network and an operational amplifier circuit. The drain and the source of the first JFET and the second JFET are electrically connected to the room-temperature end component through the cross-temperature connection cable, and a signal source is connected between the gate of the first JFET and the gate of the second JFET through a shielded differential twisted pair. The structure aims to reduce the equivalent input current noise in the signal readout with a very high impedance temperature ratio and reduce the low-temperature thermal load.

The application belongs to the technical field of power supply, and particularly relates to a power supply control method and system, electronic equipment and storage medium. The method comprises the following steps: acquiring setting data from a memory, an upper computer or a device panel as a setting value; collecting sampling data through a high-speed analog-to-digital converter, and performing high-speed digital signal processing by using a programmable logic chip, and then performing stable voltage, stable current and stable power control; acquiring control parameters corresponding to the load characteristics closest to the current setting value from the storage data as the initial data of starting up, or quickly searching for the corresponding output real-time tracking reference value and the intermediate state value of loop control; and through closed-loop control, the output reaches the setting value for different load characteristics. The application reduces the design difficulty of analog circuit, improves the response characteristics, and is convenient for realizing higher performance power supply control; meanwhile, the signal processing can be dynamically realized by adjusting the register parameters, which is convenient for automatic calibration and mass production.

This invention discloses an integrated high-voltage, high-current power distribution circuit using an external PNP transistor, belonging to the field of analog circuit design. It includes a high-voltage LDO module, a current detector, a digital controller, a digital current converter, and an external PNP transistor. The output of the error amplifier is simultaneously connected to the gates of MOSFET PM1 and PM2. The drain of MOSFET PM2 is connected to the input of the current detector, which is connected to a rise-fall counter in the digital controller. The rise-fall counter is connected to a digital-to-analog converter in the digital current converter, which is connected to a transconductance amplifier. The output of the transconductance amplifier is connected to the gate of MOSFET NM1, and the drain of MOSFET NM1 is connected to the base of transistor Q1 in the external PNP transistor. This invention achieves an integrated power distribution scheme by connecting an external PNP transistor and an LDO chip in parallel, achieving optimal results in power distribution and board area optimization. It has a simple structure, low cost, and well meets current needs.

This application discloses a computing system to simulate a circuit design describing an electronic device with a plurality of functional verification tests, separately collect samples of performance data during simulation of the circuit design for each of the functional verification tests, and generate test databases for each of the functional verification tests. Each of the test databases include samples for a corresponding functional verification test. The computing system can merge the samples of performance data in the test databases for the functional verification tests. The computing system can filter the merged samples of performance data into a subset of the merged samples of performance data based, at least in part, on profile filtering commands, and generate a profile presentation including the subset of the merged samples of performance data. The profile presentation, when displayed, can annunciate portions of the circuit design corresponding to at least one performance hotspot.

The invention belongs to the field of radio frequency integrated circuits, and particularly provides a frequency self-adaptive variable capacitance circuit of a microwave radio frequency band and application of the frequency self-adaptive variable capacitance circuit so as to meet the broadband design requirement of a radio frequency circuit. The invention provides an on-chip integrated frequency self-adaptive variable capacitance circuit which is completely based on microwave and analog circuit design and can be directly applied to various modules to realize self-adaptive change of capacitance along with frequency, so that the bandwidth of various modules is expanded; any other extra consumption except for the loss caused by the change of the capacitance Q value is not caused; meanwhile, the frequency self-adaptive variable capacitance circuit is applied to an output matching network of the radio frequency power amplifier, so that the broadband design of the radio frequency power amplifier is realized.

The application discloses a kind of non-functional device identification method in analog circuit design diagram, according to the netlist file of analog circuit, the component information and node information of analog circuit are extracted, traverse component dictionary set, short-circuit device is judged according to node information, then root node is selected, node tree is generated based on each root node respectively, Tarjan algorithm is used to identify cut point in analog circuit, according to cut point and make it become the subnode of cut point, carry out path search, the component on the path is used as non-functional component, short-circuit device and non-functional component are collected, and the final non-functional component set is obtained.The application can automatically identify non-functional component in analog circuit according to analog circuit diagram, reduce the fault number that analog circuit needs simulation, so as to shorten the time of analog circuit fault simulation.

This invention provides methods, systems, and programs that enable efficient circuit design. [Solution] An analog circuit design method using a large-scale language model, comprising the steps of: the large-scale language model receiving natural language input including information related to circuit specifications; the large-scale language model selecting knowledge information based at least on the input; the large-scale language model generating information necessary for circuit simulation based at least on at least a portion of the selected knowledge information; the circuit simulator executing a circuit simulation and generating information on the simulation results based at least on the necessary information; and the large-scale language model generating circuit design evaluation information based at least on at least a portion of the simulation results.

The present invention discloses a method for performing design space exploration, design optimization, and fine-tuning of analog circuits using a machine learning (ML) model. The method includes designing a base analog circuit, collecting SPICE simulation data for a random number of combinations of input, output, and process, voltage and temperature conditions, generating the data set from the simulation results, training the ML model using the generated dataset, identifying dominant circuit components in the base analog circuit configuration using Pearson correlation coefficients, generating from the trained machine learning model, a group of candidate analog circuit designs based on boundary conditions and desired specifications, and from the group of candidates calculating the candidate circuit that meets all the optimization criteria and the boundary conditions. The method further includes fine-tuning the optimized circuit by re-optimizing it for one or more specific sets of input, output, or PVT conditions to bring its specifications to the desired values.

The invention belongs to the technical field of machining, and particularly relates to a method for accurately driving a target vibration mode of an ultrasonic broaching machine, which comprises the following steps of: S1, designing a band-pass filter, carrying out a frequency sweep test, determining an axial modal bandwidth and carrying out thermal drift compensation; s2, realizing a digital filter, and optimizing a transition zone by adopting a Kaiser Window (Kaiser Window); a filter coefficient is quantized into a 18-bit fixed-point number format, so that the calculation efficiency during hardware implementation is improved; the FPGA is used for accelerating the filter, and the FIR filter is designed and has a linear phase characteristic so as to ensure that the signal is not distorted due to the filtering process; a standby analog circuit design is designed to serve as a supplement of a digital filter, and more redundancy and stability are provided. The broach vibration mode can be accurately driven, the purity of axial vibration is remarkably improved, the radial vibration suppression ratio is increased, and the machining precision and stability of ultrasonic equipment are further improved.

The utility model discloses a current source circuit, a chip and electronic equipment, and belongs to the field of analog circuit design. The current source circuit comprises a current mirror unit, and the current mirror unit comprises a first switching tube and a second switching tube which are connected in series between an input voltage node and a grounding node; the third switch tube and the fourth switch tube are connected in series between the input voltage node and the grounding node, the driving end of the third switch tube is electrically connected with the driving end of the first switch tube, and the driving end of the second switch tube is electrically connected with the driving end of the fourth switch tube; the resistive element is arranged on a current path between the first switching tube and the second switching tube; and / or a resistive element is arranged on a current path between the third switch tube and the fourth switch tube, the resistive element is arranged on the current path between the switch tubes in the current mirror unit, the amplitude of the noise current on the current path can be attenuated, the modulation effect of the noise current on the output current is reduced, and therefore the current output precision is improved.

Methods, systems, and devices for tuning a set of simulation parameters associated with a design verification environment are described that include: simulating a circuit design according to a set of simulation parameters; providing, to a machine learning network, an indication of functional coverage results associated with simulating the circuit design according to the set of simulation parameters; receiving an output in response to the machine learning network processing the functional coverage results; and simulating the circuit design based on a recommended set of simulation parameters, wherein simulating the circuit design based on the recommended set of simulation parameters includes generating a set of component signals associated with satisfying a target functional coverage statement. In some aspects, the output includes: the target functional coverage statement associated with the circuit design; and the recommended set of the simulation parameters.

A semiconductor structure including first finfet cells and second finfet cells. Each of the first finfet cells has an analog fin boundary according to analog circuit design rules, and each of the second finfet cells has a digital fin boundary according to digital circuit design rules. The semiconductor structure further includes first circuits formed with the first finfet cells, second circuits formed with the second finfet cells, and third circuits formed with one or more of the first finfet cells and one or more of the second finfet cells.

The invention discloses an LDO (Low Dropout Regulator) short-circuit protection circuit, an LDO chip and electronic equipment thereof, and relates to the technical field of analog circuit design, and the LDO short-circuit protection circuit comprises a detection module which is used for detecting the output state of the LDO chip and generating a short-circuit judgment signal when the output is short-circuited; the time sequence control module is connected with the detection module, responds to the short circuit judgment signal and generates a periodic pulse signal with a fixed high-level pulse width and a variable low-level pulse width; the soft start module is connected with the time sequence control module and is used for being enabled when the periodic pulse signal is at a low level, outputting a soft start signal to increase the output current and outputting an enable signal when the soft start signal reaches a threshold value; the time sequence control module is configured to disable the soft start module to maintain a first current limiting state during a high level period of the periodic pulse signal; during the low level period, the soft start module is enabled to enter a second current limiting state; in response to the enable signal, the switch is periodically switched between a first current limiting state and a second current limiting state in a short circuit state.

The utility model discloses a threshold value self-adaption liquid level detection device which comprises a control panel, a single chip microcomputer arranged on the control panel, an excitation probe interface, a detection probe interface, an excitation circuit and a detection adjusting circuit. According to the utility model, the detection threshold value is automatically adjusted according to the solution characteristics, the hysteresis interval problem which lags behind the input quantity change when the output quantity changes is eliminated, the accurate judgment is realized, and the stability is high; meanwhile, an analog circuit design is adopted, and the manufacturing cost is low.

The invention discloses a method for generating and verifying a standard cell library of an analog circuit, and relates to the technical field of analog circuit design. The method comprises the following steps: acquiring various types of standard unit requirements required in circuit design; drawing initial layout data for at least one type according to the requirement of a standard unit; generating other types of standard unit layout data through an automatic tool; integrating the initial layout data and the standard cell layout data of other types into a unified standard cell library; and performing consistency verification on each standard unit in the standard unit library by adopting a verification tool. According to the method, standard cell layouts are drawn and generated for various process types, and circuit symbols and layouts are automatically integrated into a unified standard cell library by utilizing a script tool; and carrying out layout and circuit consistency verification and design rule check by adopting a batch verification mode to ensure that the layout conforms to a process specification. The design efficiency and quality of the standard cell library are effectively improved, and a reliable basis is provided for analog circuit design.

This invention relates to the field of analog circuit design technology and discloses a method for anomaly identification and feature selection of multi-source heterogeneous data. It involves generating and optimizing a custom multi-parameter, multi-constraint circuit topology within an analog circuit environment, using an analog integrated circuit netlist as graph theory input. This method uses a multi-constraint custom circuit, taking an initial circuit structure as graph theory input, predicting the size of the analog integrated circuit using maximum likelihood estimation, and updating the simulated netlist as the graph theory input. Through comparison, the size is continuously updated, ultimately achieving automatic generation of the circuit structure from the desired structure to the final structure. Through state observation, a graph neural network model is used to optimize the circuit topology, ultimately outputting a highly feasible circuit topology whose performance parameters can reach or even surpass those of manually designed analog integrated circuits.

The invention belongs to the field of integrated circuit computer aided design / electronic design automation, and particularly relates to a value decomposition multi-agent reinforcement learning and domain randomization method which is used for solving the problem of design migration of a constrained complex system-level analog circuit. According to the method, a layered multi-agent reinforcement learning architecture is adopted, and an agent network and a hybrid network are respectively used for modeling the value of a sub-circuit and the overall value of a system-level circuit; multi-agent training is carried out under a randomized circuit working condition by adopting a domain randomization technology, so that the method can be quickly migrated to different circuit working points. The invention belongs to a fast migration algorithm for an analog circuit. The algorithm has relatively high simulation efficiency and operation time efficiency for migration optimization of a complex system-level analog circuit.

The embodiment of the present application provides a kind of digital temperature sensor, comprising: temperature sensing circuit, temperature determination circuit and voltage processing circuit consisting of voltage-driven analog device.Electric voltage processing circuit is electrically connected to the power supply end of digital temperature sensor, can utilize the volt-ampere characteristic of analog device to stabilize power supply voltage, and provide stable voltage processing after power supply voltage for temperature sensing circuit and temperature sensing circuit;Temperature sensing circuit can generate the temperature of the device to be measured corresponding to the signal to be measured;Temperature determination circuit can determine the temperature of the device to be measured according to the signal to be measured, realize the measurement of the temperature of the device to be measured.The embodiment of the present application designs suitable digital voltage domain voltage processing circuit using analog circuit, which can reduce the power supply voltage fluctuation of digital temperature sensor, help to reduce the influence of power supply voltage fluctuation on the temperature measurement accuracy of digital temperature sensor, and further help to improve the temperature measurement accuracy of digital temperature sensor.