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ROM structure and method for writing in INTEL HEX file

A file and architecture technology, applied in the field of ROM structure, can solve the problem of not being able to provide enough memory data for the host of the single-chip microcomputer, reducing the working efficiency of the single-chip microcomputer of the RISC system, etc., to achieve the effect of reducing resources

Inactive Publication Date: 2008-12-17
EAST CHINA NORMAL UNIV
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Problems solved by technology

In this way, it is impossible to provide enough memory data to the MCU host in one clock cycle, which reduces the work efficiency of the RISC system MCU for pipeline operation.

Method used

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  • ROM structure and method for writing in INTEL HEX file
  • ROM structure and method for writing in INTEL HEX file
  • ROM structure and method for writing in INTEL HEX file

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Embodiment Construction

[0023] 1. The structure of ROM

[0024] Dual-channel RAM is integrated in the FPGA chip, which can be combined into ROM. In the embodiment of the present invention, the dual-channel RAM module inside the FPGA is used to form a ROM with single address input and multiple data output, that is, when the ROM is read, an address signal is input and multiple continuous data are output.

[0025] Existing dual-channel RAM modules such as figure 1 display, including A and B channels. Among them, WEA and WEB are the write signals of the two channels of the input RAM respectively. ENA and ENB are respectively the enable signals of the two channels of the input RAM. SSRA and SSRB are respectively the reset signals of the two channels of the input RAM. CLKA and CLKB are the clock signals of the two channels of the input RAM respectively. ADDRA and ADDRB are the address signals of the two channels of the input RAM respectively. DIA and DIB are the data signals of the two channels of th...

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Abstract

The invention discloses an ROM structure and a method for writing an INTEL HEX file. The ROM is composed of n groups of RAMs, each group comprises eight dual-channel RAMs, each dual-channel RAM comprises an A channel and a B channel, and an identical address is respectively set for the address signals addrA and addrB of the A channel and the B channel of each RAM in each group; the address signals addrA and addrB input to the RAMs in each group are determined according to the address signals input to the ROM; the RAMs in each group respectively output data with two bytes; the n groups of the RAMs output data with 2*n bytes. The method for writing the INTEL HEX file by using the ROM structure is as follows: encoding and data padding are performed to the INTEL HEX file; and then data mapping is performed. By adopting the ROM structure and the method, a plurality of continuous data can be output after one address signal is input, and the ROM structure and the method are suitable for the single-chip microcomputer of the RISC architecture.

Description

technical field [0001] The invention relates to a semiconductor memory, in particular to a ROM (read only memory) structure suitable for a RISC (Reduced Instruction Set Computer) architecture single-chip microcomputer. The present invention also relates to a method for writing an INTEL HEX (data information arranged by address proposed by Intel Corporation) file into the above-mentioned ROM structure. Background technique [0002] The characteristic of ROM is that the user can only read the information in it when using it, and cannot modify or write new information. The information in the storage unit is written once by the manufacturer during production or written by the user through a programmer. The message does not disappear after shutdown. [0003] The ROM of the single-chip microcomputer is generally used to store the control program, so it is also called the program memory. After the microcontroller system is initialized, it can execute the control program in the RO...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/02
Inventor 金乃咏韩菲
Owner EAST CHINA NORMAL UNIV
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