24 results about "Processor frequency" patented technology

The invention belongs to the technical field of thermal management and performance regulation and control of a computer hardware system, and particularly discloses a temperature and performance coordinated regulation and control method of an MODT mainboard central processing unit. The entropy production rate of the system is calculated in real time in combination with a thermodynamic entropy production evaluation mechanism, and pre-cooling or advanced frequency reduction pulse type regulation and control are triggered when entropy production exceeds the threshold; meanwhile, a biological rhythm simulation mechanism is introduced, high-frequency and low-frequency alternating periodic oscillation control is carried out on the frequency of the processor in a millisecond-level window, the two mechanisms cooperatively act on the power management unit, and microsecond-level voltage regulation and heat dissipation driving linkage is achieved. According to the technical scheme, on the premise that the hardware cost is not increased, the energy efficiency performance, the transient heat dissipation capacity and the long-term operation reliability of the system under the high dynamic load are improved.

This invention discloses a method and system for detecting and correcting mismatches in time slices and processor frequencies between task groups, relating to the field of automatic control and regulation of computer system resources, specifically a collaborative closed-loop correction method for operating system scheduling and processor frequency control. The method identifies a target task group and a control task group, statistically analyzes the average effective time slices and average effective frequencies of the two task groups within an observation window, constructs time slice differences and frequency differences, and calculates a mismatch index based on the service quality deviation of the target task group to determine the mismatch mode. Correction actions are generated for different modes, performing time slice parameter compensation on the target task group and / or applying frequency constraint compensation to its running processor. Stability is ensured through upper bounds on amplitude, trigger frequency limits, hysteresis / cooling, and abnormal backoff, thereby reducing long-tail latency, frame drop risk, and unnecessary power consumption under mixed loads.

A electronic apparatus manufacturing apparatus includes at least two transporters transporting process products, a processor performing a manufacturing process on a process product transported by at least one of the at least two transporters, a processor measurer disposed on the processor to measure a processor vibration of the processor, and a controller calculating a processor frequency response of the processor based on the processor vibration and adjusting a velocity and a position of each transporter and / or a number of transporters arranged in one area among the at least two transporters based on the processor frequency response.

The application provides a neural network dynamic exit lightweight method and system for multiple continuous inferences, comprising: step 1: constructing a neural network-based inference model, predicting the position of network exit for each inference within a preset small time range, and accordingly predicting the calculation configuration, the calculation configuration comprising frequency and voltage; for multiple inferences within a preset large time range, performing processor frequency and voltage calibration through residual inference workload and time constraints; step 2: performing the neural network according to the predicted and calibrated calculation configuration, thereby realizing dynamic voltage and frequency adjustment. Compared with a classic deep learning network, the application can realize energy saving up to 63.8%, while ensuring that multiple neural network inferences are completed within a specified time, the inference can be terminated in advance through early exit to obtain accurate results, and the calculation and energy costs are reduced.

This application discloses a processor frequency modulation method, apparatus, device, and computer program product, belonging to the field of processors. The method includes: performing load tracking on each processor in the processor cluster based on the task attributes of the tasks running in the processor cluster, obtaining the processor utilization of each processor, wherein the processor cluster includes at least one processor, and different task attributes correspond to different load tracking methods; determining the target operating frequency of the processor cluster based on the processor utilization of each processor in the processor cluster; and adjusting the operating frequency of each processor in the processor cluster to the target operating frequency. Using the solution provided in this application for processor frequency modulation can reduce power consumption while ensuring performance.

The application discloses a program energy efficiency optimization method and system based on stage division and multi-stage cooperation, and the method comprises the following steps: obtaining a profiling call tree of a target program, and initializing a current level as a maximum level of the profiling call tree; extracting a node set of the current level, extracting effective nodes, extracting features, and determining a stage type of the effective nodes; adding a binary tuple formed by a node name of each effective node and the stage type into a selected stage set S; constructing a stage feature matrix for the selected stage set S of the profiling call tree, and predicting an optimal frequency combination of the target program by using a pre-trained multi-stage cooperative energy efficiency optimization model. The application aims to realize optimal processor frequency configuration of each stage of a program under the condition that the global performance constraint is met, and significantly optimize the total processor energy consumption of the program under the premise that the execution performance is not lost.

Processor frequency control for expected demand is described. In one or more implementations, an apparatus includes a processing system that executes instructions for satisfying a workload demand for a current window of time, and a power management circuit that controls a processor frequency of the processing system based on one or more characteristics of the workload demand for an earlier window of time. In at least one example, a system includes a memory including executable instructions of a workload, and a processor that executes the instructions for a second window of time according to a processor frequency that is controlled based on one or more characteristics of the instructions for a first window of time.

The invention relates to a device for manufacturing an electronic device and a method for manufacturing an electronic device. The apparatus comprises: at least two conveyors for conveying a process product; a processor performing a manufacturing process on the process product conveyed by at least one of the at least two conveyors among the process products; a processor measurer provided on the processor to measure a processor vibration of the processor; and a controller calculating a processor frequency response of the processor based on the processor vibration, and adjusting a speed and / or a position of at least one of the at least two transmitters and / or a number of transmitters arranged in one zone based on the processor frequency response.

This invention relates to the field of energy efficiency management technology, specifically to a hierarchical computing power management and dynamic frequency adjustment method for a fingerprint mouse, and a fingerprint mouse itself. Applied to a fingerprint mouse comprising a main control chip, a fingerprint module, and a password processing chip, the method, executed by the main control chip, includes: acquiring operating indicators; determining a target operating mode based on the operating indicators, the target operating mode including at least a working state and a low-power state; when in the working state, accelerating the level based on the operating indicators; dynamically adjusting at least one frequency parameter according to the target computing power level, the frequency parameters including at least the main control processor frequency and / or bus frequency and / or peripheral operating frequency; during the execution of fingerprint or password processing tasks, processing the task according to a preemptive scheduling method, with a higher scheduling priority than the fingerprint and password processing tasks; this invention enables hierarchical computing power collaborative management in a fingerprint mouse that balances low power consumption, fast authentication, and smooth interaction.

The embodiment of the invention provides a server resource scheduling method, electronic equipment and a storage medium. The method comprises the following steps: creating and loading a scheduling program in a user mode, and scanning a processor topology to generate a scheduling domain based on a non-uniform memory access node; loading the program into a memory to complete initialization of a kernel scheduler, generating a scheduling callback function and associating the scheduling callback function to realize interaction between a user mode and a kernel mode; kernel load information is obtained in real time and shared to a user mode program, a scheduling decision instruction is determined by the user mode program, and scheduling domain extension and processor frequency adjustment are executed to complete scheduling. The method can improve scheduling flexibility, optimize resource utilization, effectively improve server performance, reduce energy consumption and adapt to a dynamic load scene of a cloud data center.

The application relates to the technical field of terminal security, in particular to a game security real-time monitoring system based on artificial intelligence and big data, which comprises a time beat monitoring module, which is used for extracting a game client reading time tag instruction value, dividing the reading time tag instruction value by a processor frequency value, obtaining a hardware beat period number, and extracting an operating system process system time return value. In the application, local tampering intrusion events and current game client running time steps are extracted, a replacement reset action is implemented to generate a countermeasure reset time beat, a conventional system interface calling operation is directly discarded for a kernel communication link, communication connection is forced to be switched to a more bottom-layer system calling interface, a connection request packet data is issued under the countermeasure reset time beat, and a local intrusion takeover feedback instruction is acquired, control right is seized at the bottom layer of the operating system, a malicious process intervention path is cut off, and real-time countermeasure success rate in a high confrontation interactive scene is improved.

The invention relates to the technical field of network communication, and specifically discloses an NFV-oriented switch virtualization resource scheduling system. The system comprises a resource state sensing module, a multi-target decision engine, a dynamic frequency adjustment module and a resource allocation execution module. According to the method, by constructing the multi-objective decision engine, the maximization of the total throughput of the system and the minimization of the total power consumption of the system are determined as parallel optimization objectives, and a traditional single-performance-oriented scheduling normal form is changed fundamentally. The engine generates a Pareto optimal resource allocation strategy by solving an energy efficiency and performance balance model, so that a system can intelligently balance performance and energy consumption in a high-concurrency service scene, blind soaring of processor frequency and invalid dissipation of energy are effectively avoided, and the system performance and energy consumption are improved. The energy use efficiency of the data center is obviously improved; and the operation cost is reduced.

The application discloses a notebook multi-scene adaptive power consumption regulation method and system, relates to the technical field of notebook computer power consumption intelligent management, and comprises the following steps: collecting and processing multi-dimensional running information such as the load of a processor, the memory usage, the peripheral connection state and the user activity type in real time, and processing the multi-dimensional running information into a standardized state feature vector; inputting the feature vector into a pre-trained real-time scene recognition model; the model outputs a multi-level scene label combination composed of a primary scene label and a secondary detailed activity label; the system queries a preset power consumption strategy library according to the combined label, acquires and executes a corresponding initial regulation strategy, and the strategy content covers a processor frequency benchmark, core scheduling preference, a screen refresh rate range and background process resource limitation. The method realizes dynamic and accurate adaptive regulation of power consumption by intelligently identifying specific use scenes and matching fine strategies, and effectively improves the energy efficiency and user experience of the device under different use situations.

This invention relates to the field of deep learning technology, specifically disclosing a method for optimizing the energy efficiency of AI computing devices based on deep learning. The method includes the following steps: allocating a dedicated hardware computing partition for the AI ​​computing task to be executed and initiating the acquisition of real-time power consumption sensor data streams; acquiring the processor frequency sequence and the performance throughput sequence reflecting the task progress of the hardware computing partition; calculating a real-time energy efficiency ratio sequence based on the real-time power consumption sensor data stream and the performance throughput sequence; matching the processor frequency sequence and the real-time energy efficiency ratio sequence to construct a coordinate point sequence; retrieving a benchmark energy efficiency curve matching the current computing task and the current running stage from a pre-built task energy efficiency benchmark library; determining the target frequency adjustment value based on the coordinate point sequence and the benchmark energy efficiency curve, and generating a frequency adjustment command. This invention can achieve a better balance between performance and energy consumption.

This invention discloses a processor dynamic frequency adjustment method, device, and computer-readable storage medium. The method includes: when the real-time frame rate value fps_curr is less than the target frame rate value target_fps, calculating the next-order processor frequency value next_freq according to nextFreq = ((fps_max / fps_curr-2) + 0.25) * max_freq_support * m; and transmitting the processor frequency value next_freq to a dynamic frequency adjustment system cpufrq-driver, so that the dynamic frequency adjustment system cpufrq-driver adjusts the frequency according to the processor frequency value next_freq. This achieves an adaptive dynamic game frequency control scheme. In low-load game scenarios, it reduces power consumption while ensuring a smooth experience, while responding promptly to frequency increases during high-load game events, greatly improving the flexibility of dynamic frequency control and enhancing the user's gaming experience.

This invention discloses a dynamic processor power management method on a RISC-V system, comprising: collecting operational state characteristic data of the RISC-V system; performing temperature threshold determination based on the operational state characteristic data; performing representation learning on the system's operational state through a system meta-state learner to obtain a latent vector; performing frequency decision-making based on the latent vector through an intelligent frequency regulator; outputting frequency adjustment actions; and executing the frequency adjustment actions to achieve dynamic adjustment of the RISC-V processor's operating frequency. This invention aims to solve the problems of lag response, insufficient adjustment accuracy, and poor adaptability in existing RISC-V system processor power management. By collecting multi-dimensional system state data and combining meta-state representation learning and deep reinforcement learning, it achieves intelligent dynamic adjustment of the processor frequency, reducing power consumption and avoiding overheating while ensuring system performance, thereby improving the energy efficiency and operational stability of the RISC-V system.

This application provides a processor operation control method, components, and a readable storage medium, relating to the field of processor control technology. This application utilizes multiple wake-up units, each responsible for monitoring at least one task to be run. The target wake-up unit, upon detecting a target task, sends a processor wake-up signal to the frequency control unit, including a target frequency requirement code corresponding to the target task. The frequency control unit then determines the target processor frequency that meets the performance requirements of the target task based on the target requirement code. Finally, it directly wakes up the target CPU, which is currently in a dormant state, according to the target processor frequency. This allows the awakened target CPU to directly execute the target task at the target processor frequency, effectively improving the problems of power consumption waste and slow response time when the CPU is woken from a dormant state.

The invention discloses a program energy efficiency optimization method and system based on stage division and multi-stage collaboration, and the method comprises the steps: obtaining a parsing call tree of a target program, and carrying out the initialization setting of a current hierarchy as the maximum hierarchy of the parsing call tree; extracting a node set of the current level, extracting effective nodes, extracting features and determining stage types of the effective nodes; adding a two-tuple formed by the node name and the stage type of each effective node into a selected stage set S; and constructing a stage feature matrix for the selected stage set S of the analysis call tree, and predicting the stage feature matrix by using a pre-trained multi-stage collaborative energy efficiency optimization model to obtain an optimal frequency combination of the target program. According to the method, the minimum processor energy consumption and the optimal processor frequency configuration meeting global performance constraints in each stage of the program are realized, and the total processor energy consumption of program operation is remarkably optimized on the premise of ensuring that the execution performance is not lost.

Methods and systems for managing cooling of a data processing system. In particular, active cooling using a fan controlled by an embedded controller is provided in a data processing system having a processor installed on a system on a chip (SoC) that is originally only capable of providing passive cooling to the data processing system through throttling of the processor. The system temperature of the data processing system may be communicated from the SoC to the embedded controller using an application digital signal processor (ADSP) configured to communicate with the embedded controller using an inter-integrated circuit (I2C) / improved inter-integrated circuit (I3C) interface.

The invention relates to the technical field of packet switching, in particular to a software-defined industrial switch system based on a multi-core processor, which comprises a control mapping module, a core group configuration module, a path adjustment module, a channel scheduling module and a frequency control cutting module. According to the method, quantitative identification of task depth and execution complexity is realized through hierarchical tagging processing of a control task path structure, and a multi-class mapping relation between tasks and cores is constructed in combination with performance characteristics of a multi-core processor, so that the resource matching accuracy and scheduling flexibility are improved; based on a task execution state, access and interruption characteristics are extracted, path offset behaviors are dynamically identified, real-time kernel redistribution is completed, the continuity and scheduling balance of a task execution process are guaranteed, a priority and channel state mapping mechanism is introduced in the aspect of communication path selection, linkage constraint and cutting optimization of processor frequency and resource distribution are realized, and the task execution efficiency is improved. And the adaptability of the system to complex working conditions and the communication load management capability are enhanced.

Embodiments of the present application provide a kind of mood recognition method, electronic equipment and storage medium, belong to artificial intelligence technical field.The method comprises: according to the processor frequency, the power level of the pre-set electronic equipment is evaluated.Original mood recognition model is divided into intermediate model section.According to the power level, the target sparsity of each intermediate model section is calculated, and the intermediate model section is compressed to obtain compressed model section according to the target sparsity.According to the processor processing bit width, the weight of compressed network is grouped to obtain weight grouping, and the weight grouping is packaged as target model section.Determine current model section from each target model section, load current model section to the shared memory of pre-set electronic equipment, carry out mood recognition based on pre-set face image by current model section, and eliminate the model section of last loading from shared memory.This application can be compatible with electronic equipment of different hardware configurations, to realize the efficient local operation of mood recognition.

The application discloses a kind of energy consumption optimal processor frequency prediction method and system based on support vector machine, the present application includes the original data of performance monitoring counter value, running time, processor energy consumption, processor frequency and processor power under different parallelism, different scale, different processor frequency of different programs;For original data, construct data set and target vector according to the preset custom running time and energy consumption constraint condition;Design objective function;Parameter tuning and training evaluation are carried out to support vector machine model;Processor frequency prediction is carried out to target program using trained support vector machine model, and the processor frequency of optimal energy consumption is obtained.The present application aims to deal with the problem that the inappropriate processor frequency setting during program running leads to low energy consumption, through the energy consumption optimal processor frequency prediction based on support vector machine, ensure that application program can obtain its optimal processor frequency before loading, improve program running energy efficiency.

The embodiment of the invention provides an emotion recognition method, electronic equipment and a storage medium, and belongs to the technical field of artificial intelligence. The method comprises the following steps: evaluating the computing power level of preset electronic equipment according to processor frequency; segmenting the original emotion recognition model into middle model segments; and calculating a target sparse rate of each intermediate model section according to the computing power level, and compressing the intermediate model sections according to the target sparse rates to obtain compressed model sections. And grouping the compression network weight according to the processing bit width of the processor to obtain a weight group, and packaging the weight group into a target model segment. And determining a current model segment from each target model segment, loading the current model segment to a shared memory of a preset electronic device, performing emotion recognition based on a preset face image through the current model segment, and removing a previous model segment loaded to the shared memory from the shared memory. The method and the device can be compatible with electronic equipment with different hardware configurations, so that efficient local operation of emotion recognition is realized.