42 results about "Processor frequency" patented technology

The invention discloses an energy consumption optimal processor frequency prediction method and system based on a support vector machine. The method comprises the steps of obtaining original data of performance monitoring counter values, running time, processor energy consumption, processor frequency and processor power of different programs under different parallelism degrees, different scales and different processor frequencies; constructing a data set and a target vector for the original data according to preset self-defined operation time and energy consumption constraint conditions; designing a target function; performing parameter tuning and training evaluation on the support vector machine model; and performing processor frequency prediction on the target program by using the trained support vector machine model to obtain the processor frequency with optimal energy consumption. The method aims at solving the problem that energy consumption is low due to improper processor frequency setting during program running, it is guaranteed that the optimal processor frequency for application program running can be obtained before the application program is loaded through energy consumption optimal processor frequency prediction based on the support vector machine, and the program running energy efficiency is improved.

The invention discloses an intelligent cabin processor frequency adjusting method, system and device and a medium, and relates to the technical field of automobile intellectualization, and the method comprises the steps: obtaining a plurality of multi-mode sensor data of a vehicle-mounted intelligent cabin, and the current load data and the current temperature data of a processor; inputting the data into a load prediction model so as to output a load prediction result of the processor; classifying a plurality of pieces of sensor data into each priority queue, and if target sensor data classified into a target priority queue exists, obtaining delay time of the target priority queue; if the load prediction result is larger than a preset load threshold value, the current temperature data is smaller than a preset temperature safety threshold value, and the delay time is larger than or equal to a preset delay time threshold value, the processor is triggered to enter a temporary overclocking state; and after the processor enters the temporary overclocking state, adjusting the computing power frequency of the processor so as to increase the computing power frequency and maintain the computing power frequency for a target duration.

The invention belongs to the technical field of thermal management and performance regulation and control of a computer hardware system, and particularly discloses a temperature and performance coordinated regulation and control method of an MODT mainboard central processing unit. The entropy production rate of the system is calculated in real time in combination with a thermodynamic entropy production evaluation mechanism, and pre-cooling or advanced frequency reduction pulse type regulation and control are triggered when entropy production exceeds the threshold; meanwhile, a biological rhythm simulation mechanism is introduced, high-frequency and low-frequency alternating periodic oscillation control is carried out on the frequency of the processor in a millisecond-level window, the two mechanisms cooperatively act on the power management unit, and microsecond-level voltage regulation and heat dissipation driving linkage is achieved. According to the technical scheme, on the premise that the hardware cost is not increased, the energy efficiency performance, the transient heat dissipation capacity and the long-term operation reliability of the system under the high dynamic load are improved.

The present invention relates to the field of computer application technologies, and specifically discloses a dual-clock multi-core embedded concurrent timing simulation method and apparatus. The method includes: determining the core rate of each core in a multi-core embedded system and simulation events to be simulated; determining the global virtual clock rate of a global virtual clock according to the core rates of all cores; dividing the global virtual clock rate by the core rate to obtain the core clock rate ratio of each core's local virtual clock relative to the global virtual clock; and sequentially determining whether each core needs to execute simulation in each global virtual clock cycle according to the ratio between the current cycle number of the global virtual clock and the core clock rate ratios of each core, so as to simulate the simulation events through the cores that need to execute simulation in each global virtual clock cycle. The present invention solves the problem of core speed mismatch and simulation error caused by different core processor frequencies.

This invention discloses a method and system for detecting and correcting mismatches in time slices and processor frequencies between task groups, relating to the field of automatic control and regulation of computer system resources, specifically a collaborative closed-loop correction method for operating system scheduling and processor frequency control. The method identifies a target task group and a control task group, statistically analyzes the average effective time slices and average effective frequencies of the two task groups within an observation window, constructs time slice differences and frequency differences, and calculates a mismatch index based on the service quality deviation of the target task group to determine the mismatch mode. Correction actions are generated for different modes, performing time slice parameter compensation on the target task group and / or applying frequency constraint compensation to its running processor. Stability is ensured through upper bounds on amplitude, trigger frequency limits, hysteresis / cooling, and abnormal backoff, thereby reducing long-tail latency, frame drop risk, and unnecessary power consumption under mixed loads.

A electronic apparatus manufacturing apparatus includes at least two transporters transporting process products, a processor performing a manufacturing process on a process product transported by at least one of the at least two transporters, a processor measurer disposed on the processor to measure a processor vibration of the processor, and a controller calculating a processor frequency response of the processor based on the processor vibration and adjusting a velocity and a position of each transporter and / or a number of transporters arranged in one area among the at least two transporters based on the processor frequency response.

The application provides a neural network dynamic exit lightweight method and system for multiple continuous inferences, comprising: step 1: constructing a neural network-based inference model, predicting the position of network exit for each inference within a preset small time range, and accordingly predicting the calculation configuration, the calculation configuration comprising frequency and voltage; for multiple inferences within a preset large time range, performing processor frequency and voltage calibration through residual inference workload and time constraints; step 2: performing the neural network according to the predicted and calibrated calculation configuration, thereby realizing dynamic voltage and frequency adjustment. Compared with a classic deep learning network, the application can realize energy saving up to 63.8%, while ensuring that multiple neural network inferences are completed within a specified time, the inference can be terminated in advance through early exit to obtain accurate results, and the calculation and energy costs are reduced.

The invention discloses a server and a processor heat dissipation method, relates to the technical field of computers, and aims to avoid large temperature difference of different processors caused by manufacturing tolerance or an independent heat conduction path by arranging a radiator shared by a plurality of processors, thereby being beneficial to reducing frequency reduction of the processors. Besides, flow guide fan covers are respectively arranged between the radiator and the plurality of fans, and the flow guide directions of the flow guide fan covers and the rotating speeds of the fans are dynamically adjusted through the management controller, so that the temperatures of the plurality of processors are equivalent, and the frequency reduction of the processors can be further reduced. Therefore, the cooperative computing performance of the server is improved from two aspects.

This application discloses a processor frequency modulation method, apparatus, device, and computer program product, belonging to the field of processors. The method includes: performing load tracking on each processor in the processor cluster based on the task attributes of the tasks running in the processor cluster, obtaining the processor utilization of each processor, wherein the processor cluster includes at least one processor, and different task attributes correspond to different load tracking methods; determining the target operating frequency of the processor cluster based on the processor utilization of each processor in the processor cluster; and adjusting the operating frequency of each processor in the processor cluster to the target operating frequency. Using the solution provided in this application for processor frequency modulation can reduce power consumption while ensuring performance.

The invention provides a frequency reduction processing method and device, electronic equipment and a storage medium, and relates to the technical field of computers. The method comprises the steps of determining current first calculation performance data of a processor; determining whether the processor has underclocking according to the first calculation performance data; when frequency reduction of the processor is determined, determining a target frequency reduction level according to the first calculation performance data; and closing at least one service corresponding to the target frequency reduction level. According to the method and the device, whether the processor has underclocking or not can be detected based on the first calculation performance data, and corresponding service closing can be realized according to the current underclocking level when underclocking occurs, so that the influence of underclocking of the processor on AI core service operation can be reduced, stable operation of a system can be effectively guaranteed, and the service quality of the AI core service is improved. And user experience is improved.

The application discloses a program energy efficiency optimization method and system based on stage division and multi-stage cooperation, and the method comprises the following steps: obtaining a profiling call tree of a target program, and initializing a current level as a maximum level of the profiling call tree; extracting a node set of the current level, extracting effective nodes, extracting features, and determining a stage type of the effective nodes; adding a binary tuple formed by a node name of each effective node and the stage type into a selected stage set S; constructing a stage feature matrix for the selected stage set S of the profiling call tree, and predicting an optimal frequency combination of the target program by using a pre-trained multi-stage cooperative energy efficiency optimization model. The application aims to realize optimal processor frequency configuration of each stage of a program under the condition that the global performance constraint is met, and significantly optimize the total processor energy consumption of the program under the premise that the execution performance is not lost.

Processor frequency control for expected demand is described. In one or more implementations, an apparatus includes a processing system that executes instructions for satisfying a workload demand for a current window of time, and a power management circuit that controls a processor frequency of the processing system based on one or more characteristics of the workload demand for an earlier window of time. In at least one example, a system includes a memory including executable instructions of a workload, and a processor that executes the instructions for a second window of time according to a processor frequency that is controlled based on one or more characteristics of the instructions for a first window of time.

The invention discloses a processor frequency determination method and device and electronic equipment, and belongs to the technical field of computers.The method can comprise the steps that under the condition that first input of a user to an application icon is received, first starting information of a first stage of application starting is obtained; according to the first startup information of the first stage, the reference processor frequency and the expected startup completion time of the application, determining a second processor frequency of the electronic equipment in a second stage of application startup; wherein the first starting information comprises a first load proportion, the first load proportion is the share of the load of the first stage in the total load of application starting, the reference processor frequency is the average processor frequency of the last application starting stage, and the expected starting completion time is the time of ending application starting animation display.

The invention discloses a processor frequency determination method and device and a chip, and belongs to the technical field of image processing. The method comprises the following steps: acquiring performance data of an image frame drawing task; obtaining the actual operation time length of the image frame drawing task in a historical time window; determining the effective operation duration of the image frame drawing task in the historical time window according to the performance data and the actual operation duration; and determining the task load of the image frame drawing task according to the effective operation duration, and determining the operation frequency of a central processing unit according to the task load.

The invention relates to a device for manufacturing an electronic device and a method for manufacturing an electronic device. The apparatus comprises: at least two conveyors for conveying a process product; a processor performing a manufacturing process on the process product conveyed by at least one of the at least two conveyors among the process products; a processor measurer provided on the processor to measure a processor vibration of the processor; and a controller calculating a processor frequency response of the processor based on the processor vibration, and adjusting a speed and / or a position of at least one of the at least two transmitters and / or a number of transmitters arranged in one zone based on the processor frequency response.

This invention relates to the field of energy efficiency management technology, specifically to a hierarchical computing power management and dynamic frequency adjustment method for a fingerprint mouse, and a fingerprint mouse itself. Applied to a fingerprint mouse comprising a main control chip, a fingerprint module, and a password processing chip, the method, executed by the main control chip, includes: acquiring operating indicators; determining a target operating mode based on the operating indicators, the target operating mode including at least a working state and a low-power state; when in the working state, accelerating the level based on the operating indicators; dynamically adjusting at least one frequency parameter according to the target computing power level, the frequency parameters including at least the main control processor frequency and / or bus frequency and / or peripheral operating frequency; during the execution of fingerprint or password processing tasks, processing the task according to a preemptive scheduling method, with a higher scheduling priority than the fingerprint and password processing tasks; this invention enables hierarchical computing power collaborative management in a fingerprint mouse that balances low power consumption, fast authentication, and smooth interaction.

The embodiment of the invention provides a server resource scheduling method, electronic equipment and a storage medium. The method comprises the following steps: creating and loading a scheduling program in a user mode, and scanning a processor topology to generate a scheduling domain based on a non-uniform memory access node; loading the program into a memory to complete initialization of a kernel scheduler, generating a scheduling callback function and associating the scheduling callback function to realize interaction between a user mode and a kernel mode; kernel load information is obtained in real time and shared to a user mode program, a scheduling decision instruction is determined by the user mode program, and scheduling domain extension and processor frequency adjustment are executed to complete scheduling. The method can improve scheduling flexibility, optimize resource utilization, effectively improve server performance, reduce energy consumption and adapt to a dynamic load scene of a cloud data center.

An embodiment of the present application discloses a task running method, device, storage medium, and terminal. The method includes: detecting the current working temperature of the terminal, determining the idle duty ratio corresponding to at least one task on the processor at the working temperature, determining the initial running duration corresponding to each task, calculating the processor running duration and the processor idle duration corresponding to each task based on the initial running duration and the idle duty ratio corresponding to each task, and sequentially running each task according to the processor running duration and the processor idle duration corresponding to each task. The present application can make the processor run corresponding tasks during the processor running duration and be in an idle state during the processor idle duration, avoiding the situation in the related art where the processor frequency is limited to achieve the purpose of cooling due to the increase in the terminal temperature, resulting in the terminal becoming stuck. The present application can relieve the terminal temperature while ensuring that the terminal does not become stuck.

The disclosure relates to techniques for selecting processor frequencies. Apparatuses, systems, and techniques for selecting processing unit frequencies. In at least one embodiment, an operating frequency of the one or more integrated circuits is dynamically adjusted based at least in part on a dynamically measured maximum throughput of the one or more integrated circuits.

The application relates to the technical field of terminal security, in particular to a game security real-time monitoring system based on artificial intelligence and big data, which comprises a time beat monitoring module, which is used for extracting a game client reading time tag instruction value, dividing the reading time tag instruction value by a processor frequency value, obtaining a hardware beat period number, and extracting an operating system process system time return value. In the application, local tampering intrusion events and current game client running time steps are extracted, a replacement reset action is implemented to generate a countermeasure reset time beat, a conventional system interface calling operation is directly discarded for a kernel communication link, communication connection is forced to be switched to a more bottom-layer system calling interface, a connection request packet data is issued under the countermeasure reset time beat, and a local intrusion takeover feedback instruction is acquired, control right is seized at the bottom layer of the operating system, a malicious process intervention path is cut off, and real-time countermeasure success rate in a high confrontation interactive scene is improved.

The present application discloses a frequency control system, method, device, electronic device and storage medium, which relates to the field of computer technology. Through the present application, based on the statistics and analysis of the repetitive cycle law at the time point of the first system management interrupt, the triggering time of the second system management interrupt is set, thereby reducing unnecessary interrupts and reducing the negative impact of frequent interrupts on processor performance. After the second system management interrupt is triggered, the number of instructions executed by the processor between the two system management interrupts is obtained, the occupancy rate is calculated, and the processor frequency is adjusted in combination with the frequency control scheme corresponding to different occupancy rate intervals, so that the processor frequency adjustment is more in line with the actual load requirements. The problem of performance degradation caused by frequent interruptions is avoided, and the frequency is flexibly adjusted according to the actual workload, thereby solving the technical problem of frequent system management interrupts reducing processor performance in the prior art, and achieving the technical effect of achieving system energy saving while ensuring processor performance.

The invention relates to the technical field of network communication, and specifically discloses an NFV-oriented switch virtualization resource scheduling system. The system comprises a resource state sensing module, a multi-target decision engine, a dynamic frequency adjustment module and a resource allocation execution module. According to the method, by constructing the multi-objective decision engine, the maximization of the total throughput of the system and the minimization of the total power consumption of the system are determined as parallel optimization objectives, and a traditional single-performance-oriented scheduling normal form is changed fundamentally. The engine generates a Pareto optimal resource allocation strategy by solving an energy efficiency and performance balance model, so that a system can intelligently balance performance and energy consumption in a high-concurrency service scene, blind soaring of processor frequency and invalid dissipation of energy are effectively avoided, and the system performance and energy consumption are improved. The energy use efficiency of the data center is obviously improved; and the operation cost is reduced.

The application discloses a notebook multi-scene adaptive power consumption regulation method and system, relates to the technical field of notebook computer power consumption intelligent management, and comprises the following steps: collecting and processing multi-dimensional running information such as the load of a processor, the memory usage, the peripheral connection state and the user activity type in real time, and processing the multi-dimensional running information into a standardized state feature vector; inputting the feature vector into a pre-trained real-time scene recognition model; the model outputs a multi-level scene label combination composed of a primary scene label and a secondary detailed activity label; the system queries a preset power consumption strategy library according to the combined label, acquires and executes a corresponding initial regulation strategy, and the strategy content covers a processor frequency benchmark, core scheduling preference, a screen refresh rate range and background process resource limitation. The method realizes dynamic and accurate adaptive regulation of power consumption by intelligently identifying specific use scenes and matching fine strategies, and effectively improves the energy efficiency and user experience of the device under different use situations.

The invention discloses a frequency control system, method and device, electronic equipment and a storage medium, and relates to the technical field of computers.According to the frequency control method and device, a repetition period rule is counted and analyzed based on a first system management interruption time point, and a second system management interruption triggering opportunity is set, so that unnecessary interruption is reduced, and the efficiency is improved. And the negative influence of frequent interruption on the performance of the processor is reduced. After the second system management interrupt is triggered, the number of instructions executed by the processor between two times of system management interruptions is obtained, the occupancy rate is calculated, and processor frequency adjustment is carried out in combination with frequency control schemes corresponding to different occupancy rate intervals, so that processor frequency adjustment better meets actual load requirements. The problem of performance reduction caused by frequent interruption is avoided, and the frequency is flexibly adjusted according to the actual workload, so that the technical problem of processor performance reduction caused by frequent system management interruption in the prior art can be solved, and the technical effect of system energy conservation is achieved while the processor performance is ensured.

This invention relates to the field of deep learning technology, specifically disclosing a method for optimizing the energy efficiency of AI computing devices based on deep learning. The method includes the following steps: allocating a dedicated hardware computing partition for the AI ​​computing task to be executed and initiating the acquisition of real-time power consumption sensor data streams; acquiring the processor frequency sequence and the performance throughput sequence reflecting the task progress of the hardware computing partition; calculating a real-time energy efficiency ratio sequence based on the real-time power consumption sensor data stream and the performance throughput sequence; matching the processor frequency sequence and the real-time energy efficiency ratio sequence to construct a coordinate point sequence; retrieving a benchmark energy efficiency curve matching the current computing task and the current running stage from a pre-built task energy efficiency benchmark library; determining the target frequency adjustment value based on the coordinate point sequence and the benchmark energy efficiency curve, and generating a frequency adjustment command. This invention can achieve a better balance between performance and energy consumption.

This invention discloses a processor dynamic frequency adjustment method, device, and computer-readable storage medium. The method includes: when the real-time frame rate value fps_curr is less than the target frame rate value target_fps, calculating the next-order processor frequency value next_freq according to nextFreq = ((fps_max / fps_curr-2) + 0.25) * max_freq_support * m; and transmitting the processor frequency value next_freq to a dynamic frequency adjustment system cpufrq-driver, so that the dynamic frequency adjustment system cpufrq-driver adjusts the frequency according to the processor frequency value next_freq. This achieves an adaptive dynamic game frequency control scheme. In low-load game scenarios, it reduces power consumption while ensuring a smooth experience, while responding promptly to frequency increases during high-load game events, greatly improving the flexibility of dynamic frequency control and enhancing the user's gaming experience.

Apparatuses, systems, and techniques to select frequency of a processing unit. In at least one embodiment, an operating frequency of one or more integrated circuits is dynamically adjusted based, at least in part, on a dynamically measured maximum throughput of the one or more integrated circuits.

The invention provides a processor frequency adjusting method. The method is applied to electronic equipment comprising a display screen. The method comprises the following steps: acquiring a screen state of a display screen, wherein the screen state comprises a folded state and an unfolded state; a processor frequency is determined according to the screen state. In different screen states, the electronic equipment has different requirements on the performance of a processor and has different heat dissipation capacities. Therefore, by implementing the method, the electronic equipment can take the screen state as a basis for adjusting the frequency of the processor, lower processor frequency is used when the electronic equipment is in the folded state, heat is reduced, and power consumption is reduced. And a relatively high processor frequency is used in the unfolded state, so that the performance is ensured, jamming is prevented, and the overall experience of a user is improved.

The invention relates to the technical field of wireless communication, in particular to a cooperative reasoning resource allocation method and system oriented to a large language model in a wireless network, and in each cooperative reasoning round, a base station obtains channel gains from each terminal # imgabs0 # to the base station, generates a resource allocation scheme, and sends the resource allocation scheme to the base station; each terminal # imgabs1 # performs terminal side large language model # imgabs2 # reasoning according to the terminal side central processing unit frequency, the uplink transmission bandwidth, the uplink transmission power allocation scheme and the base station side cache allocation scheme, and calculates a terminal side output sequence # imgabs3 #, and the base station receives the terminal side output sequence and the cache sequence and sends the cache sequence to the terminal side. And reasoning the base station side large language model # imgabs4 # according to the frequency allocation scheme of the base station side central processing unit to obtain output lexical elements, and sending the output lexical elements to each terminal. According to the method, large language model cooperative reasoning in the wireless network is accelerated by utilizing calculation and cache resources at a base station side, and cooperative reasoning time delay is reduced.

The disclosure describes a method and system for dynamic frequency scaling of multi-core processor in wireless communication networks. The method comprising: transmitting, by a network node (NN), core-load data and a plurality of key indicators of each core group of a plurality of core groups in the multi-core processor to a central management entity (CME); receiving, by the NN, a core-load prediction model associated for each core group from the CME; determining, by the NN, an estimated core-load data for each core group using the associated core-load prediction model and determining, by the NN, a maximum estimated core-load data among the estimated core-load data of each core group; and determining, by the NN, an optimum multi-core processor frequency for the network node based on the maximum estimated core-load data.