Clock generator circuit and related method for generating output clock signal

Abstract

The present invention discloses a clock generator circuit for generating an output clock signal. The clock generator circuit includes: a random frequency code generator for generating a frequency code randomly, wherein the random frequency code generator is clocked by a first clock signal; an accumulator electrically connected to the random frequency code generator, for generating a selection code by accumulating the frequency code, wherein the accumulator is clocked by the first clock signal; a first multiplexer electrically connected to the accumulator, for selecting one of a plurality of reference clock signals as the first clock signal according to the selection code; and a toggle circuit electrically connected to the first multiplexer, being clocked by the first clock signal for generating the output clock signal. The invention can generate output clock signals selected with much more frequency.

Description

technical field [0001] The present invention relates to a clock generation circuit, in particular to a clock generation circuit and method for generating output clock signals with multiple selected frequency characteristics. Background technique [0002] In today's common electronic systems, different integrated circuits (integrated circuit, IC) often have the need to perform synchronous (synchronous) operation. In this type of system, it must be based on a basic system clock (or a synchronous pulse ), to generate periodic clock signals in an appropriate way to drive different circuit functions to operate synchronously. [0003] The figure is a schematic diagram of a clock generation circuit in the prior art. figure 1 The clock generating circuit 100 shown includes a multiplexer 120 , an accumulator 125 , and a toggle circuit 140 . The accumulator 125 is composed of a register 130 and an adder 150 , and the register 130 is realized by a first D-flip flop 130 . The trigger...

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Problems solved by technology

In the prior art clock generation circuit 100, the generated output clock signal C OUT The selectable frequencies are limited, and the number of selectable frequencies is mainly determined by the number N of reference clock signals input to the multiplexer 120. There is no way to provide more frequency options according to the needs of the back-end circuit. output clock signal

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