Data-latching circuit adopting phase selector

Abstract

The invention provides a data-latching circuit. The data-latching circuit comprises a first data-latching unit, a second data-latching unit, a third data-latching unit and a phase selector, wherein the first data-latching unit is used for latching a first input data according to a first clock signal and outputting a first output data; the second data-latching unit is used for latching the first output data according to a second clock signal and outputting a second output data; the third data-latching unit is used for latching the second output data according to a third clock signal and outputting an output data; and the phase selector is coupled with the second data-latching unit and used for generating the second clock signal according to the phase relation between the first and the third clock signals and outputting the second clock signal to the second data-latching unit.

Description

technical field [0001] The invention relates to a data receiving device and method, in particular to a data latch circuit and method using a phase selector. Background technique [0002] In some interface systems or larger chips, maintaining the same clock in each part of the chip is the biggest challenge to the system. Usually, the existing chips contain digital circuit parts and analog circuit parts, and the digital circuit part occupies almost 100% of the chip. Mainly more than 80% of the area, so when the circuit designer plans the timing problem of the entire integrated circuit, it is usually the digital circuit design to estimate the driving capability of the clock output from the digital circuit part and the capacitance generated by the circuit layout and routing effect, and by analyzing and estimating the delay between the clock that finally reaches the analog circuit part and the clock output by the original clock source, and finally solves the problem of clock phas...

AI Technical Summary

Problems solved by technology

However, if the setup time and data hold time of the flip-flop are not enough, the lock circuit 100 still has the problem of data error, such as figure 2 shown, when flip-flop 104 samples data D 1 to get data D 2 , if the flip-flop 102 is sampling the input data D in , then due to the data D 1 The logic value of is changing, so the data D obtained by flip-flop 104 2 It cannot be guaranteed to be correct, which will further affect the final output data D out correctness

In other words, even if the existing data latch circuit 100 uses two consecutive data latch elements (that is, flip-flops 104, 106) to improve the accuracy of the sampled data, it is still affected by the first clock CLK 1 with the second clock CLK 2 has the chance of sampling error due to the influence of improper phase relationship between

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