Low-dropout linear regulator (LDO) circuit and method with overcharge protection function

Abstract

The embodiment of the present invention discloses a low-dropout linear regulator LDO circuit and method with an overcharge protection function, which belongs to the technical field of integrated circuit design. The LDO circuit includes a voltage stabilizing circuit and an overcharge protection circuit; the overcharge protection circuit includes an RC circuit, a first resistor, a first switch, and a second resistor; the first port of the RC circuit is connected to the output port of the voltage stabilizing circuit, the second port of the RC circuit is connected to the first port of the first switch, and the third port of the RC circuit is grounded; the first port of the first resistor is connected to the output port of the voltage stabilizing circuit, the second port of the first resistor is connected to the second port of the first switch; the first port of the second resistor is connected to the third port of the first switch, and the second port of the second resistor is grounded; the voltage of the output port in the voltage stabilizing circuit is less than the breakdown voltage of the load in the voltage stabilizing circuit. The embodiment of the present invention can reduce the voltage output by the output port of the voltage stabilizing circuit when powered on, thereby protecting the load hung on the voltage stabilizing circuit.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of integrated circuit design, and in particular to a low dropout linear regulator (LDO) circuit and method with an overcharge protection function. Background Art

[0002] Figure 1 A classic LDO (Low Drop Out Linear Voltage Regulator) circuit is shown, which includes an OPA (Operational Amplifier), a PMOS (P-Channel Metal Oxide Semiconductor Field Effect Transistor) tube M1, a resistor R1, a resistor R2 and a capacitor C1, wherein an inverting input port of the OPA inputs a reference voltage VBG, an output port V1 is connected to a gate of M1, a source of M1 is connected to a power supply VDD, a drain of M1 is connected to an output node VO and one port of R1 respectively, another port of R1 is connected to one port of R2, a connection node of R1 and R2 is connected to a non-inverting input port of the OPA, one port of C1 is connected to an output node VO, and another port of C1 and another port of R2 are grounded together.

[0003] Before power-on, the voltage of all nodes in the above LDO circuit is 0V; when power-on, due to the fast power-on speed and the limited bandwidth of OPA, the voltage of V1 does not have time to adjust and rises, causing M1 to be turned on. In this way, the excessively high VDD will be passed to VO through M1. Although it is generally believed that this fast transient power-on overcharge is a short-term output overcharge voltage, it has little effect on the load on the output port of the LDO circuit in a short time. However, for an LDO circuit with a wide power supply voltage input range, the output voltage may be overcharged very high in an instant. If the device mounted on the load is a low-voltage device, then in the case of repeated power-on, the low-voltage device can still be damaged by the continuous impact of excessive surge voltage.

[0004] In order to perform overcharge protection when powering on, an existing solution is to increase the capacitance of C1. Since C1 responds to AC at the moment of powering on, C1 will form a low on-resistance and divide the voltage with M1, thereby lowering the output voltage on VO. However, too large a capacitance is not easy to drive and will affect the stability of the LDO circuit. Summary of the invention

[0005] The embodiment of the present invention provides a low voltage dropout linear regulator (LDO) circuit and method with overcharge protection function, which is used to solve the problem that when overcharge protection is performed by increasing the capacitance value of the capacitor in the LDO circuit, the capacitor is not easy to drive and affects the stability of the LDO circuit. The technical solution is as follows:

[0006] In a first aspect, a low-dropout linear regulator (LDO) circuit with an overcharge protection function is provided, wherein the LDO circuit comprises a voltage stabilization circuit and an overcharge protection circuit;

[0007] The overcharge protection circuit includes a resistor-capacitor RC circuit and a voltage divider circuit, and the voltage divider circuit includes a first resistor, a first switch and a second resistor;

[0008] The first port of the RC circuit is connected to the output port of the voltage stabilizing circuit, the second port of the RC circuit is connected to the first port of the first switch, and the third port of the RC circuit is grounded;

[0009] A first port of the first resistor is connected to an output port of the voltage stabilizing circuit, and a second port of the first resistor is connected to a second port of the first switch;

[0010] The first port of the second resistor is connected to the third port of the first switch, and the second port of the second resistor is grounded;

[0011] Wherein, the voltage of the output port in the voltage stabilizing circuit is lower than the breakdown voltage of the load in the voltage stabilizing circuit.

[0012] In an optional implementation, the first switch is a first P-channel metal oxide semiconductor field effect transistor (PMOS) or a first PNP transistor, the resistance of the first resistor is zero, and the resistance of the second resistor is greater than or equal to zero.

[0013] In an optional embodiment, the first switch is the first PMOS tube, then the gate of the first PMOS tube is the first port of the first switch, the source of the first PMOS tube is the second port of the first switch, and the drain of the first PMOS tube is the third port of the first switch; or, the first switch is the first PNP-type transistor, then the base of the first PNP-type transistor is the first port of the first switch, the emitter of the first PNP-type transistor is the second port of the first switch, and the collector of the first PNP-type transistor is the third port of the first switch.

[0014] In an optional implementation, the first switch is a first N-channel metal oxide semiconductor field effect transistor (NMOS) or a first NPN transistor, the resistance of the first resistor is greater than or equal to zero, and the resistance of the second resistor is zero.

[0015] In an optional embodiment, the first switch is the first NMOS transistor, then the gate of the first NMOS transistor is the first port of the first switch, the drain of the first NMOS transistor is the second port of the first switch, and the source of the first NMOS transistor is the third port of the first switch; or, the first switch is the first NPN-type transistor, then the base of the first NPN-type transistor is the first port of the first switch, the collector of the first NPN-type transistor is the second port of the first switch, and the emitter of the first NPN-type transistor is the third port of the first switch.

[0016] In an optional embodiment, the RC circuit includes a third resistor and a first capacitor connected in series;

[0017] The first port of the third resistor is the first port of the RC circuit;

[0018] A connection node between the second port of the third resistor and the first port of the first capacitor is a second port of the RC circuit;

[0019] The second port of the first capacitor is the third port of the RC circuit.

[0020] In an optional implementation, the size of the time constant of the RC circuit is positively correlated with the effect of overcharge suppression.

[0021] In an optional implementation, the voltage stabilizing circuit includes an operational amplifier OPA, a second switch, a fourth resistor, a fifth resistor and a second capacitor;

[0022] The inverting input port of the OPA inputs a reference voltage, and the output port of the OPA is connected to the gate of the second switch;

[0023] The source of the second switch is connected to a power source, and the drain of the second switch is connected to an output port of the voltage stabilizing circuit and a first port of the fourth resistor respectively;

[0024] The second port of the fourth resistor is connected to the first port of the fifth resistor, and the connection node of the fourth resistor and the fifth resistor is connected to the same-direction input port of the OPA;

[0025] A first port of the second capacitor is connected to an output port of the voltage stabilizing circuit, and a second port of the second capacitor and a second port of the fifth resistor are grounded together.

[0026] In a second aspect, an overcharge protection method for an LDO circuit is provided, which is used in the LDO circuit with overcharge protection function as described above, and the method includes:

[0027] When the LDO circuit is powered on, the first switch is in an open state under the control of the RC circuit, the voltage stabilizing circuit and the voltage divider circuit are connected, and the voltage at the output port in the voltage stabilizing circuit is less than the breakdown voltage of the load in the voltage stabilizing circuit;

[0028] When the LDO circuit is powered on, the first switch is in a closed state under the control of the RC circuit, and the voltage stabilizing circuit and the voltage divider circuit are disconnected.

[0029] The beneficial effects of the technical solution provided by the embodiment of the present invention include at least:

[0030] Since the LDO circuit includes a voltage stabilizing circuit and an overcharge protection circuit, wherein the overcharge protection circuit includes an RC circuit and a voltage divider circuit, and the voltage divider circuit includes a first resistor, a first switch, and a second resistor; the first port of the RC circuit is connected to the output port of the voltage stabilizing circuit, the second port of the RC circuit is connected to the first port of the first switch, and the third port of the RC circuit is grounded; the first port of the first resistor is connected to the output port of the voltage stabilizing circuit, and the second port of the first resistor is connected to the second port of the first switch; the first port of the second resistor is connected to the third port of the first switch, and the second port of the second resistor is grounded; in this way, when the LDO circuit is powered on, the first switch is in an open state under the control of the RC circuit, the voltage stabilizing circuit and the voltage divider circuit are connected, and the voltage divider circuit can divide the voltage with the voltage stabilizing circuit, thereby reducing the voltage output by the output port of the voltage stabilizing circuit when powered on, so that the voltage of the output port is less than the breakdown voltage of the load hung on the voltage stabilizing circuit, thereby achieving the effect of protecting the load hung on the voltage stabilizing circuit; when the LDO is powered on, the first switch is in a closed state under the control of the RC circuit, the voltage stabilizing circuit and the voltage divider circuit are disconnected, and the voltage divider circuit no longer affects the voltage stabilizing circuit.

[0031] Compared with overcharging protection by increasing the capacitance value of the second capacitor in the voltage stabilizing circuit, since the capacitance value of the second capacitor of the LDO circuit in this embodiment is relatively small, the problem of the capacitor being difficult to drive and affecting the stability of the LDO circuit will not occur. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 It is a schematic diagram of an LDO circuit in the prior art;

[0034] Figure 2 is a schematic diagram of an LDO circuit with an overcharge protection function in one embodiment of the present invention;

[0035] Figure 3 is a schematic diagram of an LDO circuit with an overcharge protection function in one embodiment of the present invention;

[0036] Figure 4 is a schematic diagram of an LDO circuit with an overcharge protection function in one embodiment of the present invention;

[0037] Figure 5 The present invention is a flowchart of an overcharge protection method for an LDO circuit in one embodiment of the present invention. DETAILED DESCRIPTION

[0038] To make the objectives, technical solutions and advantages of the embodiments of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0039] Please refer to Figure 2 , Figure 2 An LDO circuit with an overcharge protection function is shown. The LDO circuit includes a voltage stabilization circuit 210 and an overcharge protection circuit 220 .

[0040] The voltage regulator circuit 210 is used for low voltage difference linear voltage regulation, and the overcharge protection circuit 220 is used for overcharge protection when the LDO circuit is powered on, so as to avoid damage to the load mounted on the LDO. The output port VO of the voltage regulator circuit 210 is connected to the input port of the overcharge protection circuit 220.

[0041] The overcharge protection circuit 220 includes an RC circuit 221 and a voltage divider circuit 222. The voltage divider circuit 222 includes a first resistor R4, a first switch S1, and a second resistor R5. The first switch S1 may be a PMOS transistor or a PNP transistor, or the first switch S1 may be an NMOS (N-Channel Metal Oxide Semiconductor Field Effect Transistor) transistor or an NPN transistor, and the resistance values ​​of the first resistor R4 and the second resistor R5 may be adjusted according to the type of the first switch S1, as described below.

[0042] The connection relationship between the components in the RC circuit 221 and the voltage divider circuit 222 is described below.

[0043] A first port of the RC circuit 221 is connected to the output port VO of the voltage stabilizing circuit 210, a second port of the RC circuit 221 is connected to the first port of the first switch S1, and a third port of the RC circuit 221 is grounded; a first port of the first resistor R4 is connected to the output port VO of the voltage stabilizing circuit 210, a second port of the first resistor R4 is connected to the second port of the first switch S1; a first port of the second resistor R5 is connected to the third port of the first switch S1, and a second port of the second resistor R5 is grounded.

[0044] The working principle of the LDO circuit is briefly described below. In this embodiment, when the LDO circuit is powered on, the RC circuit 221 can identify the overcharge pulse and send a control signal to the first switch S1. The first switch S1 is in an open state under the control of the control signal. In this way, the voltage stabilizing circuit 210 and the voltage divider circuit 222 are connected, and the voltage divider circuit 222 can divide the voltage with the voltage stabilizing circuit 210, thereby reducing the voltage output by the output port VO of the voltage stabilizing circuit 210, so that the voltage of the output port VO is less than the breakdown voltage of the load hung on the voltage stabilizing circuit 210, thereby protecting the load hung on the voltage stabilizing circuit 210. After the LDO circuit is powered on, the RC circuit 221 does not receive the overcharge pulse, and will not send a control signal to the first switch S1. Therefore, the first switch S1 is in a closed state under the control of the RC circuit 221, and the voltage stabilizing circuit 210 and the voltage divider circuit 222 are disconnected, and the voltage divider circuit 222 no longer affects the voltage stabilizing circuit 210.

[0045] It should be noted that in this embodiment, the capacitance value of the second capacitor C1 in the voltage stabilizing circuit 210 is not increased, so the problem of the capacitor being difficult to drive and affecting the stability of the LDO circuit will not occur.

[0046] In addition, since the overcharge protection circuit 220 is a passive circuit, compared with adding an active circuit after the voltage stabilizing circuit 210, it will not cause additional current consumption when performing overcharge protection, and can also reduce the complexity of the LDO circuit.

[0047] In summary, the LDO circuit with overcharge protection function of this embodiment can effectively suppress or even eliminate the influence of overcharge of the LDO circuit on the reliability of the load without causing additional current consumption, and can also reduce the complexity of the LDO circuit.

[0048] The voltage stabilizing circuit 210 in the LDO circuit may have a variety of structures. This embodiment is described by taking one of the classic structures as an example, but the structure of the voltage stabilizing circuit 210 is not limited thereto.

[0049] The voltage stabilizing circuit 210 includes an OPA, a second switch M1, a fourth resistor R1, a fifth resistor R2, and a second capacitor C1. The second switch M1 may be a PMOS transistor or a PNP transistor, and the parameters of the OPA, the second switch M1, the fourth resistor R1, the fifth resistor R2, and the second capacitor C1 may be selected according to the actual application scenario, and are not limited in this embodiment.

[0050] The inverting input port of the OPA inputs the reference voltage VBG, and the output port of the OPA is connected to the gate of the second switch M1. The reference voltage VBG is usually generated by a bandgap reference, and its value can be selected according to the actual scenario, which is not limited in this embodiment.

[0051] The source of the second switch M1 is connected to the power source VDD, and the drain of the second switch M1 is connected to the output port VO of the voltage stabilizing circuit 210 and the first port of the fourth resistor R1 respectively.

[0052] The second port of the fourth resistor R1 is connected to the first port of the fifth resistor R2, and the connection node of the fourth resistor R1 and the fifth resistor R2 is connected to the same-direction input port of the OPA. In this way, the voltage of the output port VO can be adjusted by adjusting the resistance ratio of the fourth resistor R1 and the fifth resistor R2.

[0053] The first port of the second capacitor C1 is connected to the output port VO of the voltage stabilizing circuit 210, and the second port of the second capacitor C1 and the second port of the fifth resistor R2 are grounded together. The second capacitor C1 is used for energy storage.

[0054] In conjunction with the structure of the voltage stabilizing circuit 210 , the working principle of the LDO circuit is described in detail below.

[0055] In the prior art, when the LDO circuit is powered on, the second switch M1 in the voltage regulator circuit 210 is turned on, and the resistance of the second switch M1 is small, so the output port VO of the voltage regulator circuit 210 will output a large overcharge pulse, thereby damaging the load on the LDO circuit.

[0056] In this embodiment, when the LDO circuit is powered on, the RC circuit 221 can identify the overcharge pulse and send a control signal to the first switch S1. The first switch S1 is in an open state under the control of the control signal. In this way, the voltage stabilizing circuit 210 and the voltage divider circuit 222 are connected, and the voltage can be divided by the second switch M1 through each device in the voltage divider circuit 222, thereby reducing the voltage output by the output port VO of the voltage stabilizing circuit 210, so that the voltage of the output port VO is less than the breakdown voltage of the load hung on the voltage stabilizing circuit 210, thereby achieving the effect of protecting the load hung on the voltage stabilizing circuit 210. That is, the second switch M1, the first resistor R4, the first switch S1 and the second resistor R5 are connected, and the low-resistance path strength between the output port VO and the ground can be adjusted by adjusting the resistance values ​​of the first resistor R4, the first switch S1 and the second resistor R5, so that the first resistor R4, the first switch S1 and the second resistor R5 form a very low on-resistance, so that when dividing the voltage with the second switch M1, the output voltage of the output port VO is effectively pulled down.

[0057] When the LDO circuit is powered on, the RC circuit 221 does not receive an overcharge pulse and does not send a control signal to the first switch S1. Therefore, the first switch S1 is in a closed state under the control of the RC circuit 221, and the voltage stabilizing circuit 210 and the voltage divider circuit 222 are disconnected, so that the voltage divider circuit 222 no longer affects the voltage stabilizing circuit 210.

[0058] In an optional embodiment, the sum of the resistance values ​​of the voltage divider circuit 222 may be less than or equal to or slightly greater than the resistance value of the second switch M1 in the voltage stabilizing circuit 210 when powered on. In this way, when the voltage stabilizing circuit 210 and the voltage divider circuit 222 are connected, the power supply VDD is divided according to the resistance values ​​of the second switch M1 and the voltage divider circuit 222, effectively pulling down the output voltage of the output port VO, so that the voltage of the output port VO is less than the breakdown voltage of the load connected to the voltage stabilizing circuit 210, thereby protecting the load connected to the LDO circuit.

[0059] Theoretically, the smaller the sum of the resistance values ​​of the voltage divider circuit 222 is, the better. However, considering that when the resistance value of the voltage divider circuit 222 is the limit value 0, the current between the power supply VDD and the ground is large, the current flowing through the second switch M1 may cause electromigration and burn the metal connection or the active area of ​​the second switch M1, which may cause safety hazards, and the smaller the resistance value of the voltage divider circuit 222, the larger the size of the first switch S1 will be, thereby affecting the volume of the LDO circuit. In summary, the appropriate resistance value of the voltage divider circuit 222 can be selected according to actual needs.

[0060] The RC circuit 221 is described below. The RC circuit 221 in this embodiment includes a third resistor R3 and a first capacitor C2 connected in series; the first port of the third resistor R3 is the first port of the RC circuit 221; the connection node V2 of the second port of the third resistor R3 and the first port of the first capacitor C2 is the second port of the RC circuit 221; the second port of the first capacitor C2 is the third port of the RC circuit 221.

[0061] In this embodiment, the time constant of the RC circuit 221 can also be adjusted. If the time constant is larger, the overcharge pulse that the OPA in the LDO circuit cannot respond to can be absorbed faster. In this way, when the overcharge pulse comes, the first capacitor C2 will be shorted to the ground, and the connection node V2 is a low voltage of 0V. The first port of the first switch S1 can be controlled to turn on the first switch S1. At this time, the second switch M1, the first resistor R4, the first switch S1 and the second resistor R5 are turned on. That is, the size of the time constant of the RC circuit 221 is positively correlated with the effect of overcharge suppression.

[0062] Among them, the time constant is equal to the product of the third resistor R3 and the first capacitor C2, so the time constant can be adjusted by adjusting the resistance value of the third resistor R3 and / or adjusting the capacitance value of the first capacitor C2. Theoretically, the larger the time constant, the better. However, considering that when the time constant is large, the size of the third resistor R3 and the first capacitor C2 is large, which affects the volume of the LDO circuit. On the whole, the appropriate time constant can be selected according to actual needs.

[0063] As mentioned above, the first switch S1 may be a PMOS transistor or a PNP transistor, or the first switch S1 may be an NMOS transistor or an NPN transistor. These two structures are described below.

[0064] 1) The first switch S1 is a first PMOS transistor or a first PNP transistor, the resistance of the first resistor R4 is zero, and the resistance of the second resistor R5 is greater than or equal to zero.

[0065] In this embodiment, since the resistance of the first resistor R4 is zero, the first resistor R4 can be omitted. At this time, the voltage divider circuit 222 includes a first switch S1 and a second resistor R5, and the second port of the first switch S1 is directly connected to the output port VO of the voltage stabilizing circuit 210. Please refer to Figure 3 , Figure 3 In the example, the first switch S1 is denoted as M2.

[0066] When the resistance of the voltage divider circuit 222 needs to be further reduced, the resistance of the second resistor R5 can be set to zero, that is, the second resistor R5 can be omitted. At this time, the voltage divider circuit 222 includes a first switch S1, and the second port of the first switch S1 is directly connected to the output port VO of the voltage stabilizing circuit 210, and the third port of the first switch S1 is directly grounded.

[0067] In this embodiment, the first switch S1 is a first PMOS tube, then the gate of the first PMOS tube is the first port of the first switch S1, the source of the first PMOS tube is the second port of the first switch S1, and the drain of the first PMOS tube is the third port of the first switch S1; or, the first switch S1 is a first PNP-type transistor, then the base of the first PNP-type transistor is the first port of the first switch S1, the emitter of the first PNP-type transistor is the second port of the first switch S1, and the collector of the first PNP-type transistor is the third port of the first switch S1.

[0068] 2) The first switch S1 is a first NMOS transistor or a first NPN transistor, the resistance of the first resistor R4 is greater than or equal to zero, and the resistance of the second resistor R5 is zero.

[0069] In this embodiment, since the resistance of the second resistor R5 is zero, the second resistor R5 can be omitted. At this time, the voltage divider circuit 222 includes the first switch S1 and the first resistor R4, and the third port of the first switch S1 is directly grounded. Figure 4 , Figure 4 In the example, the first switch S1 is denoted as M2.

[0070] When the resistance of the voltage divider circuit 222 needs to be further reduced, the resistance of the first resistor R4 can be set to zero, that is, the first resistor R4 can be omitted. At this time, the voltage divider circuit 222 includes a first switch S1, and the second port of the first switch S1 is directly connected to the output port VO of the voltage stabilizing circuit 210, and the third port of the first switch S1 is directly grounded.

[0071] In this embodiment, the first switch S1 is a first NMOS transistor, then the gate of the first NMOS transistor is the first port of the first switch S1, the drain of the first NMOS transistor is the second port of the first switch S1, and the source of the first NMOS transistor is the third port of the first switch S1; or, the first switch S1 is a first NPN transistor, then the base of the first NPN transistor is the first port of the first switch S1, the collector of the first NPN transistor is the second port of the first switch S1, and the emitter of the first NPN transistor is the third port of the first switch S1.

[0072] Please refer to Figure 5 , Figure 5 An overcharge protection method for an LDO circuit is shown, which is used in the above-mentioned LDO circuit with overcharge protection function, and the method includes:

[0073] Step 501, when the LDO circuit is powered on, the first switch is in an open state under the control of the RC circuit, the voltage stabilizing circuit and the voltage dividing circuit are connected, and the voltage of the output port is less than the breakdown voltage of the load connected to the voltage stabilizing circuit.

[0074] Among them, when the voltage stabilizing circuit and the voltage divider circuit are connected, the voltage divider circuit can divide the voltage with the voltage stabilizing circuit, thereby reducing the voltage output by the output port VO of the voltage stabilizing circuit when power is turned on, so that the voltage of the output port VO is less than the breakdown voltage of the load hung on the voltage stabilizing circuit, thereby achieving the effect of protecting the load hung on the voltage stabilizing circuit.

[0075] Step 502: After the LDO circuit is powered on, the first switch is in a closed state under the control of the RC circuit, and the voltage stabilizing circuit and the voltage dividing circuit are disconnected.

[0076] When the voltage stabilizing circuit and the voltage dividing circuit are disconnected, the voltage dividing circuit no longer affects the voltage stabilizing circuit.

[0077] In summary, in the overcharge protection method of the LDO circuit provided in this embodiment, the voltage divider circuit can divide the voltage with the voltage stabilizing circuit, thereby reducing the voltage output by the output port VO of the voltage stabilizing circuit when powered on, so that the voltage of the output port VO is less than the breakdown voltage of the load hung on the voltage stabilizing circuit, thereby achieving the effect of protecting the load hung on the voltage stabilizing circuit.

[0078] The above description is not intended to limit the embodiments of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.

Claims

1. A low dropout linear regulator LDO circuit with overcharge protection function, characterized in that: The LDO circuit includes a voltage stabilization circuit and an overcharge protection circuit; The overcharge protection circuit includes a resistor-capacitor RC circuit and a voltage divider circuit, and the voltage divider circuit includes a first resistor, a first switch and a second resistor; The first port of the RC circuit is connected to the output port of the voltage stabilizing circuit, the second port of the RC circuit is connected to the first port of the first switch, and the third port of the RC circuit is grounded; A first port of the first resistor is connected to an output port of the voltage stabilizing circuit, and a second port of the first resistor is connected to a second port of the first switch; The first port of the second resistor is connected to the third port of the first switch, and the second port of the second resistor is grounded; Wherein, the voltage of the output port in the voltage stabilizing circuit is lower than the breakdown voltage of the load in the voltage stabilizing circuit.

2. The LDO circuit with overcharge protection function according to claim 1, characterized in that: The first switch is a first P-channel metal oxide semiconductor field effect transistor (PMOS) or a first PNP transistor, the resistance of the first resistor is zero, and the resistance of the second resistor is greater than or equal to zero.

3. The LDO circuit with overcharge protection function according to claim 2, characterized in that: The first switch is the first PMOS tube, the gate of the first PMOS tube is the first port of the first switch, the source of the first PMOS tube is the second port of the first switch, and the drain of the first PMOS tube is the third port of the first switch; The first switch is the first PNP type transistor, then the base of the first PNP type transistor is the first port of the first switch, the emitter of the first PNP type transistor is the second port of the first switch, and the collector of the first PNP type transistor is the third port of the first switch.

4. The LDO circuit with overcharge protection function according to claim 1, characterized in that: The first switch is a first N-channel metal oxide semiconductor field effect transistor (NMOS) or a first NPN transistor, the resistance of the first resistor is greater than or equal to zero, and the resistance of the second resistor is zero.

5. The LDO circuit with overcharge protection function according to claim 4, characterized in that: The first switch is the first NMOS transistor, the gate of the first NMOS transistor is the first port of the first switch, the drain of the first NMOS transistor is the second port of the first switch, and the source of the first NMOS transistor is the third port of the first switch; The first switch is the first NPN transistor, the base of the first NPN transistor is the first port of the first switch, the collector of the first NPN transistor is the second port of the first switch, and the emitter of the first NPN transistor is the third port of the first switch.

6. The LDO circuit with overcharge protection function according to claim 1, characterized in that: The RC circuit includes a third resistor and a first capacitor connected in series; The first port of the third resistor is the first port of the RC circuit; A connection node between the second port of the third resistor and the first port of the first capacitor is a second port of the RC circuit; The second port of the first capacitor is the third port of the RC circuit.

7. The LDO circuit with overcharge protection function according to claim 6, characterized in that: The size of the time constant of the RC circuit is positively correlated with the effect of overcharge suppression.

8. The LDO circuit with overcharge protection function according to any one of claims 1 to 7, characterized in that: The voltage stabilizing circuit includes an operational amplifier OPA, a second switch, a fourth resistor, a fifth resistor and a second capacitor; The inverting input port of the OPA inputs a reference voltage, and the output port of the OPA is connected to the gate of the second switch; The source of the second switch is connected to a power source, and the drain of the second switch is connected to an output port of the voltage stabilizing circuit and a first port of the fourth resistor respectively; The second port of the fourth resistor is connected to the first port of the fifth resistor, and the connection node of the fourth resistor and the fifth resistor is connected to the same-direction input port of the OPA; A first port of the second capacitor is connected to an output port of the voltage stabilizing circuit, and a second port of the second capacitor and a second port of the fifth resistor are grounded together.

9. An overcharge protection method for an LDO circuit, characterized in that: Used in an LDO circuit with overcharge protection function as claimed in any one of claims 1 to 8, the method comprising: When the LDO circuit is powered on, the first switch is in an open state under the control of the RC circuit, the voltage stabilizing circuit and the voltage divider circuit are connected, and the voltage at the output port in the voltage stabilizing circuit is less than the breakdown voltage of the load in the voltage stabilizing circuit; When the LDO circuit is powered on, the first switch is in a closed state under the control of the RC circuit, and the voltage stabilizing circuit and the voltage divider circuit are disconnected.

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