Electronic control device and gate driving method of power semiconductor element

Abstract

In an electronic control device equipped with a power semiconductor element, the surge voltage during the switching operation of the power semiconductor element can be suppressed, and the high-reliability and low-loss electronic control device can perform the high-speed switching operation. The present invention is characterized by comprising: a microcomputer; a power semiconductor element; and a gate drive circuit that generates a gate drive current for the power semiconductor element on the basis of a command from the microcomputer, the gate drive circuit detecting a start of an operation of turning on and off a switch by detecting a change in an output voltage of the power semiconductor element, the gate drive circuit being configured to generate a gate drive current for the power semiconductor element in the switch at the time of turning on; the gate drive current is increased before the peak voltage is reached in the switching at the off time, and the gate drive current is reduced before the peak voltage is reached in the switching at the off time.

Description

Technical Field

[0001] The present invention relates to a structure and control of an electronic control device, and in particular to a gate drive circuit and a gate drive method of a power semiconductor element mounted on the electronic control device. Background Art

[0002] With the development of electronic control technology, the performance of automobiles based on electronic control has been improved in various functions and devices, including engines. In many cases, today's automobiles are equipped with more than 100 electronic control units (ECUs), which have become important components responsible for the control of various advanced technologies. These ECUs are required to be small and lightweight while also being low-cost and highly efficient.

[0003] ECUs in a broad sense, including ECUs used in advanced driver-assistance systems (ADAS), engine control units, and inverters, are generally equipped with input processing circuits that process inputs from sensors and switches, AD conversion circuits, microcomputers, power supply circuits, output processing circuits, and power semiconductor elements.

[0004] For example, in an inverter, direct current is converted into alternating current by switching power semiconductor elements such as IGBT (Insulated Gate Bipolar Transistor) and SiC-power-MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). In order to improve the conversion efficiency of the inverter, it is effective to reduce the switching loss of the power semiconductor element, but there is a trade-off relationship between the switching loss of the power semiconductor element and the surge voltage during switching, so the gate drive circuit and gate drive method of the high-efficiency power semiconductor element with less switching loss are studied.

[0005] As background technology in this technical field, there is a technology such as Patent Document 1. Patent Document 1 discloses "a drive circuit that sets the command discharge current of the gate of the switching element to monotonically increase during the main discharge period, switches the switching element to the off state by controlling the gate discharge current to the set command discharge current, and sets the command charge current of the gate of the switching element to monotonically decrease during the main charge period, switches the switching element to the on state by controlling the gate charge current to the set command charge current." (Abstract of Patent Document 1, etc.) Prior art literature Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2016-174455 Summary of the invention Problem that the invention aims to solve

[0007] The technical solution of the driving circuit described in the above-mentioned patent document 1 is: the discharge current is monotonically increased during the main discharge period, and the charging current is monotonically decreased during the main charge period. The gate driving method is a feedforward type, and the driving is performed with a constant gate current value that increases or decreases monotonically and is pre-recorded in a memory, and a constant time for starting and stopping the increase or decrease.

[0008] However, in the feedforward form of constant determined driving, it is not possible to achieve optimal driving for characteristic variations such as temperature dependence and threshold voltage of the driven power semiconductor element, and therefore there is room for improvement in the switching characteristics of the power semiconductor element.

[0009] Therefore, the object of the present invention is to provide a highly reliable and low-loss electronic control device and a gate driving method for a power semiconductor element in an electronic control device equipped with a power semiconductor element, which can suppress surge voltage during switching action of the power semiconductor element and can perform high-speed switching action. Technical means of solving problems

[0010] In order to solve the above-mentioned problem, the technical solution of the present invention comprises: a microcomputer; a power semiconductor element; and a gate drive circuit, which generates a gate drive current of the power semiconductor element according to an instruction from the microcomputer, and the gate drive circuit detects the start of the on and off action of the switch by detecting the change in the output voltage of the power semiconductor element, and in the on-time switch, the gate drive current is increased before the peak voltage is reached, and in the off-time switch, the gate drive current is reduced before the peak voltage is reached.

[0011] In addition, the present invention is a gate driving method for a power semiconductor element, and its technical solution includes: (a) a step of detecting the start of the on or off action of the switch by detecting the change in voltage between the drain terminal and the source terminal of the power semiconductor element; (b) a step of increasing the gate driving current in the switch when the power semiconductor element is turned on before the peak voltage is reached; and (c) a step of reducing the gate driving current in the switch when the power semiconductor element is turned off before the peak voltage is reached. Effects of the Invention

[0012] According to the present invention, in an electronic control device equipped with a power semiconductor element, surge voltage during switching operation of the power semiconductor element can be suppressed, and a highly reliable and low-loss electronic control device capable of high-speed switching operation and a gate driving method for the power semiconductor element can be realized.

[0013] The other objects, structures, and effects than those described above will become clear from the following description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a diagram showing a schematic structure of a gate driving circuit according to the first embodiment of the present invention. Figure 2 It is a diagram showing a schematic structure of a gate driving circuit according to a second embodiment of the present invention. Figure 3 It is a diagram showing a schematic structure of a gate driving circuit according to a third embodiment of the present invention. Figure 4 This is a timing diagram of the turn-off operation of the power semiconductor element. Figure 5 This is a timing diagram of the conduction operation of the power semiconductor element. Figure 6 It is a diagram showing a schematic structure of a gate driving circuit according to a fourth embodiment of the present invention. Figure 7 It is a diagram showing a schematic structure of an electronic control device according to a fifth embodiment of the present invention. DETAILED DESCRIPTION

[0015] Hereinafter, embodiments of the present invention will be described using the accompanying drawings. In each of the drawings, the same components are denoted by the same reference numerals, and detailed descriptions of duplicated components are omitted.

[0016] In addition, in each embodiment, the names of the terminals of the power semiconductor element are unified as gate terminal, drain terminal, and source terminal, but in the case of IGBT, the drain terminal can be replaced by the collector terminal, and the source terminal can be replaced by the emitter terminal. In addition, it is assumed that the power semiconductor element is an IGBT or SiC-power MOSFET, but all power devices that use gate voltage to control the on and off of the switch can also be used as the object, and it can also be Si-power MOSFET, GaN-power MOSFET, etc. Embodiment 1

[0017] Reference Figure 1 and Figure 4 , Figure 5 , describing an electronic control device and a gate driving method for a power semiconductor element according to a first embodiment of the present invention.

[0018] Figure 11 is a schematic diagram of the electronic control device of the present embodiment, and mainly shows the structure of the gate drive circuit 1 . Figure 4 and Figure 5 These are timing charts of the power semiconductor element 20 during the off operation and the on operation, respectively.

[0019] like Figure 1 As shown in FIG. 1 , the main components of the electronic control device of this embodiment include a microcontroller (hereinafter referred to as a "microcomputer") 10, a power semiconductor element 20, and a gate drive circuit 1. In addition, it also includes an input processing circuit, an AD conversion circuit, a power supply circuit, and an output processing circuit. Figure 1 Omitted in .

[0020] In addition, Figure 1 2 shows a configuration diagram of one arm for driving the power semiconductor element 20. Generally, in an inverter or the like, a motor is driven by using upper and lower arms of a configuration in which three-phase upper and lower arms of the one arm are connected. In this case, a gate drive circuit for six arms and a microcomputer are used to form a motor. Figure 1 Even when driven by multiple arms, the operations of each arm are the same as those of a single-phase arm, so the embodiment of the present invention will be described here based on the operation of one arm.

[0021] The microcomputer 10 outputs a PWM gate drive signal 11 to the gate drive circuit 1 .

[0022] The gate drive circuit 1 comprises: an on-drive current switching unit 32 and an off-drive current switching unit 33 for switching the gate drive current of the power semiconductor element 20; a gate on-drive unit 30 and a gate off-drive unit 31 for driving the power semiconductor element 20 by a set drive current; an output transmission unit 40 connected to the drain terminal 22 of the power semiconductor element 20; a constant voltage generating unit 41 for generating a constant voltage for output detection; a cutoff filter adjusting unit 43 and a on-filter adjusting unit 44 for filtering the voltage of the output detection terminal 42; an output cutoff detection unit 45 and an output on-detection unit 46 for respectively detecting the start of cutoff and the start of conduction of the power semiconductor element 20 using filtered signals; and an inter-insulation communication unit 12.

[0023] use Figure 1 and Figure 4 The turn-off operation of the power semiconductor element 20 of the gate drive circuit 1 of the present embodiment will be described.

[0024] When the microcomputer 10 instructs the OFF drive by the PWM gate drive signal 11 , the signal is transmitted from the low voltage part (not shown) of the microcomputer 10 to the high voltage part (not shown) of the gate drive circuit 1 through the inter-insulation communication part 12 .

[0025] When the OFF command is transmitted to the gate driving circuit 1, the gate driving current supplied from the gate ON driving unit 30 is stopped. Thereafter, the gate OFF driving unit 31 outputs the set first OFF driving current from the OFF driving current switching unit 33, and starts OFF driving of the power semiconductor element 20.

[0026] like Figure 4 As shown, as the cut-off drive starts, the voltage of the gate terminal 24 gradually decreases and becomes constant near the threshold of the power semiconductor element 20. At this time, the voltage between the drain terminal 22 and the source terminal 23 (hereinafter referred to as "output voltage"), which is the output voltage, starts to increase, and the switching at the cut-off time starts.

[0027] The output transfer unit 40 connected to the drain terminal 22 detects the increase in the output voltage as a change in the AC voltage. In the constant voltage generating unit 41, a constant DC voltage (for example, 5V) is generated to bias the output detection terminal 42. Figure 4 As shown, as the output voltage increases, the voltage of the output detection terminal 42 increases from, for example, a constant voltage of 5 V through AC detection of the increase in the output voltage.

[0028] The cutoff filter adjustment unit 43 has the functions of preventing erroneous detection due to noise in the output voltage and adjusting the delay time until switching to the second cutoff drive current (delay circuit), and filters the voltage of the output detection terminal 42 and transmits it to the output cutoff detection unit 45 .

[0029] The output cutoff detection unit 45 performs a comparison operation by comparing the voltage of the output detection terminal 42 with a reference voltage (eg, 6V) higher than a constant voltage (eg, 5V) and detects that the cutoff switch has started when the voltage of the output detection terminal 42 exceeds 6V.

[0030] Since the detection of the cut-off switch occurs only once in each cut-off instruction of the PWM gate drive signal 11, the result of one detection is latched during one PWM period and cleared in the next PWM signal. Through this action, multiple detections in one switch can be avoided, and erroneous switching of the gate drive current caused by erroneous detection due to switching noise can be prevented.

[0031] When the output cut-off detection unit 45 detects the start of the cut-off switch, the cut-off detection signal 47 is transmitted to the cut-off drive current switching unit 33. In the cut-off drive current switching unit 33, the drive current is switched from the first cut-off drive current to the second cut-off drive current with a smaller current, and the power semiconductor element 20 is driven via the gate cut-off drive unit 31. That is, in the switch at the time of cut-off, the gate drive current is reduced before reaching the peak voltage. By reducing the gate drive current to the second cut-off drive current in the cut-off switch, the cut-off surge voltage can be reduced without changing the switching speed of the output voltage change.

[0032] Here, the turn-off surge voltage depends on the type and characteristics of the power semiconductor element 20 and various parameters such as parasitic inductance and parasitic capacitance of the busbar of the power module on which the power semiconductor element 20 is mounted. Therefore, the switching timing of the effective gate drive current reduction often differs for each electronic control device.

[0033] Therefore, by adjusting the time from the change in output voltage to the switching of the gate drive current by the cutoff filter adjustment unit 43 , it is possible to adjust the optimal timing for suppressing the cutoff surge voltage caused by the switching of the gate drive current.

[0034] In addition, the cutoff filter adjustment unit 43 can be configured at any position of the path from the drain terminal 22 to the gate cutoff drive unit 31, but since it has the function of adjusting the signal delay and filtering for removing false detection caused by noise in the change of the output voltage, it is configured in the front section of the output cutoff detection unit 45 in this embodiment.

[0035] Next, use Figure 1 and Figure 5 The conduction operation of the power semiconductor element 20 of the gate drive circuit 1 of the present embodiment will be described.

[0036] When the microcomputer 10 instructs on-drive via the PWM gate drive signal 11 , a signal is transmitted from a low voltage unit (not shown) equipped with the microcomputer 10 to a high voltage unit (not shown) equipped with the gate drive circuit 1 via the inter-insulation communication unit 12 .

[0037] When the on command is transmitted to the gate drive circuit 1, the gate drive current supplied from the gate off drive unit 31 is first stopped. Then, the on drive current switching unit 32 outputs the set first on drive current, and the on drive of the power semiconductor element 20 is started.

[0038] like Figure 5 As shown, as the on-drive starts, the voltage of the gate terminal 24 gradually increases and becomes constant near the threshold of the power semiconductor element 20. At this time, the output voltage starts to drop, and the switching at the on-time starts.

[0039] The output transmission unit 40 connected to the drain terminal 22 detects the decrease in the output voltage as a change in AC voltage. Thus, the output transmission unit 40 can detect changes in the output voltage of both the on and off operations of the power semiconductor element 20 in an AC manner.

[0040] Here, the gate drive circuit 1 that drives the power semiconductor element 20 operates with the voltage of the source terminal 23 as a reference voltage, but on the other hand, the voltage between the drain terminal 22 and the source terminal 22, which is the output voltage of the power semiconductor element 20, becomes a high voltage when the power semiconductor element 20 is turned off, so a high withstand voltage structure is required in the output transmission part 40 connected to the drain terminal 22.

[0041] Therefore, in this embodiment, high-voltage capacitive coupling is used to transmit the output voltage changes of both the on and off operations of the power semiconductor element 20 as AC signals to the output transmission unit 40. By using capacitive coupling, the increase and decrease of the output voltage can be transmitted as AC signals.

[0042] like Figure 5 As shown, when the power semiconductor element 20 is turned on, the reduction in output voltage is transmitted as an AC signal through the output transmission unit 40. A constant DC voltage (e.g., 5V) is generated in the constant voltage generation unit 41, and the output detection terminal 42 is biased. The power semiconductor 20 starts to turn on, the output voltage starts to drop, and the voltage of the output detection terminal 42 starts to drop from the constant voltage (e.g., 5V) through the output transmission unit 40.

[0043] The conduction filter adjustment unit 44 has the functions of preventing erroneous detection due to noise of the output voltage and adjusting the delay time until switching to the second conduction drive current (delay circuit), and filters the voltage of the output detection terminal 42 and transmits it to the output conduction detection unit 46 .

[0044] Here, if the switching delay adjustment time of the cutoff filter adjustment unit 43 to the second cutoff drive current is the same as the switching delay adjustment time of the conduction filter adjustment unit 44 to the second conduction drive current, the cutoff filter adjustment unit 43 and the conduction filter adjustment unit 44 can also be shared.

[0045] The output conduction detection unit 46 performs a comparison operation with a reference voltage (eg, 4V) lower than a constant voltage (eg, 5V) of the output detection terminal 42, and detects that conduction switching has started when the voltage of the output detection terminal 42 is lower than 4V.

[0046] Since the detection of the on-switch occurs only once in each off-command of the PWM gate drive signal 11, the result of one detection is latched during one PWM period and cleared in the next PWM signal. This action can avoid multiple detections in one switch, and can prevent erroneous switching of the gate drive current caused by erroneous detection due to switching noise, etc.

[0047] When the output conduction detection unit 46 detects the start of the conduction switching, the conduction detection signal 48 is transmitted to the conduction drive current switching unit 32, and the drive current is switched from the first conduction drive current to the second conduction drive current with a larger current in the conduction drive current switching unit 32, and the power semiconductor element 20 is driven via the gate conduction drive unit 30. That is, in the switch at the time of conduction, the gate drive current is increased before reaching the peak voltage.

[0048] By increasing the gate drive current in the on switch to a second on drive current, Figure 5 The recovery surge of the output voltage of the arm shown does not change, and after the recovery surge ends, the voltage of the gate terminal 24 is increased, and the output voltage is rapidly decreased by rapidly turning on the switch. This can reduce the switching loss.

[0049] Here, the recovery surge voltage of the pair arm refers to the voltage generated by the recovery action of the freewheeling diode 21 generated when the current flowing forward in the freewheeling diode 21 of the power semiconductor element 20 of the pair arm is cut off, and depends on various parameters such as the parasitic inductance and parasitic capacitance of the busbar of the power module equipped with the power semiconductor element 20 and the freewheeling diode 21, etc. Therefore, the switching timing of the effective gate drive current reduction is often different for each electronic control device.

[0050] Therefore, by adjusting the time from the change in output voltage to the switching of the gate drive current by the on-filter adjustment unit 44 , it is possible to adjust the optimal timing for suppressing the recovery surge voltage to the arm caused by the switching of the gate drive current.

[0051] In addition, the conduction filter adjustment unit 44 can be configured at any position of the path from the drain terminal 22 to the gate conduction drive unit 30, but since it has the function of adjusting the signal delay and filtering for removing false detection caused by noise in the output voltage change, it is configured in the front section of the output conduction detection unit 46 in this embodiment.

[0052] In addition, the output cutoff detection unit 45 and the output conduction detection unit 46 detect the start of the cutoff switch and the conduction switch respectively, and do not need to detect them at the same time, so they can also be combined into one. In this case, the detection voltage is different when it is turned on and when it is turned off, so it is necessary to switch the detection voltage. Therefore, by integrating the gate drive circuit 1 of this embodiment into a semiconductor integrated circuit, the semiconductor chip area can be reduced, which has the effect of reducing costs.

[0053] As described above, in the electronic control device of this embodiment, the change in output voltage can be detected, and the start of the on-switch or the start of the off-switch can be detected through the output transmission unit 40 connected to the drain terminal 22 of the power semiconductor element 20 and the constant voltage generation unit 41, the output cutoff detection unit 45, the output on-detection unit 46, the cutoff filter adjustment unit 43, and the on-filter adjustment unit 44.

[0054] In the cut-off operation, after the cut-off switch starts detecting, the drive current is switched from the first cut-off drive current to the second cut-off drive current by the cut-off drive current switching unit 33, thereby reducing the cut-off surge voltage of the output voltage. Since the cut-off surge voltage can be reduced, the first cut-off drive current can be increased compared to the case where the present invention is not implemented, the cut-off switch of the power semiconductor element 20 can be made faster, and the switching loss at the time of cut-off can be reduced.

[0055] On the other hand, during the conduction operation, after the conduction switch starts detecting, the gate drive current can be increased from the first conduction drive current to the second conduction drive current by the conduction drive current switching unit 32. Thus, the gate drive current is increased after the recovery surge voltage generated in the recovery operation of the freewheeling diode 21 of the pair arm is generated, thereby not increasing the recovery surge voltage, making it possible to increase the switching speed of the output voltage and reduce the conduction switch loss.

[0056] According to the present invention, by detecting a change in the output voltage of the power semiconductor element 20 and switching the gate drive current at a good timing, it is possible to reduce the switching loss.

[0057] In addition, since the junction temperature of the power semiconductor element is reduced due to the reduction in loss, the chip area of ​​the power semiconductor element can be reduced, and the cost can also be reduced. Embodiment 2

[0058] Reference Figure 2 , describing an electronic control device and a gate driving method for a power semiconductor element according to a second embodiment of the present invention.

[0059] Figure 2 1 is a schematic diagram of the electronic control device of this embodiment, mainly showing the structure of the gate drive circuit 2. Figure 2 The gate drive circuit 2 shown is Figure 1 The configuration of the gate driving circuit 1 is shown as a circuit as a specific circuit example.

[0060] Generally, there are two types of gate drive circuits: a constant current drive method that performs gate drive with a constant current and a constant voltage drive method that generates a gate drive current with a drive voltage and a resistor. This embodiment is an embodiment of the present invention applied to the constant current drive method.

[0061] The command of the PWM gate drive signal 11 sent from the microcomputer 10 is transmitted from a low voltage unit (not shown) in which the microcomputer 10 is mounted to a high voltage unit (not shown) in which the gate drive circuit 2 is mounted via the inter-insulation communication unit 12 .

[0062] When the PWM gate drive signal 11 is a cut-off instruction, the conduction control switch 74 switches from the conduction control reference voltage 75 to the power supply voltage VCC8. As a result, the conduction control amplifier 73 drives the PMOS FET 66 to control the conduction control amplifier negative feedback terminal 72 from the conduction control reference voltage 75 to the power supply voltage VCC8 in the negative feedback operation. Through this negative feedback operation, the gate drive current at the time of conduction determined by the conduction control amplifier negative feedback terminal 72 and the resistors 64 and 65 is zero, and the gate drive current on the conduction side is cut off.

[0063] On the other hand, the cutoff control switch 78 connected to the non-inverting input of the cutoff control amplifier 77 is controlled by the inverter 76, and the non-inverting input of the cutoff control amplifier 77 is switched from the cutoff reference voltage 70 level to the cutoff control reference voltage 81. As a result, the cutoff control amplifier 77 controls the cutoff control amplifier negative feedback terminal 80 from the cutoff reference voltage 70 level to the same voltage as the cutoff control reference voltage 81 in the negative feedback operation by driving the NMOS FET 67. The gate drive current at the time of cutoff becomes a constant current determined by the voltage of the cutoff control amplifier negative feedback terminal 80 and the resistors 68 and 69, and therefore the gate drive current at the time of cutoff flows by switching the cutoff reference voltage 70 level to the cutoff control reference voltage 81 through the cutoff control amplifier negative feedback terminal 80.

[0064] Here, when the cut-off operation starts, the cut-off current switching switch 79 is turned on, and the cut-off current switching switch 84 is turned off. Through the negative feedback control of the cut-off control amplifier 77, Figure 4 The first OFF drive current shown is a current value obtained by dividing the ON control reference voltage 75 by the resistance value of the resistor 69 .

[0065] If the gate drive current on the on side and the gate drive current on the off side flow at the same time, the current from the power supply voltage VCC8 through the off reference voltage 70 flows. Therefore, when the gate drive current on the on side and the gate drive current on the off side are switched, they are temporarily cut off and then switching control is performed to prevent the through current from flowing.

[0066] Here, the constant voltage source 54 is a voltage source that outputs a constant voltage, for example, 5 V. When the power semiconductor element 20 is not in a switch that is turned on or off, the voltage between the drain terminal 22 and the source terminal 23, which is the output voltage of the power semiconductor element 20, becomes a constant voltage, so the voltage of the output detection terminal 42 becomes the same voltage as the constant voltage source 54, which is 5 V in this case.

[0067] As described in Example 1, Figure 4 At the timing shown in the timing chart of , the gate drive current for the off time flows, and the power semiconductor element 20 starts the off operation, and the output voltage of the power semiconductor element 20 increases.

[0068] Here, the capacitor 50 is connected to the drain terminal 22, and as the output voltage increases, the voltage of the output detection terminal 42 increases. The electrostatic capacitor 51 has the effect of attenuating the transmission of the output voltage to the output detection terminal 42, and can suppress excessive voltage changes of the output detection terminal 42 when the output voltage has a high voltage amplitude.

[0069] like Figure 4 As shown, the increase of the output voltage at the time of cutoff is transmitted to the output detection terminal 42, and the delay time Doff for switching the signal to the second cutoff drive current is adjusted by the resistor 55 and the capacitor 57. In addition, the resistor 55 and the capacitor 57 also act as a filter for preventing the output voltage from being erroneously detected.

[0070] When the input signal exceeds the cutoff detection reference voltage 59 , the cutoff detection comparator 61 detects a rise in the output voltage, switches the cutoff current switching switch 79 from on to off, and switches the cutoff current switching switch 84 from off to on.

[0071] Thus, the negative feedback control of the OFF control amplifier 77 causes the OFF drive current to be switched to the second OFF drive current obtained by dividing the OFF control reference voltage 81 by the resistance value of the resistors 68 and 69 .

[0072] In this way, by switching the drive current from the first cut-off drive current to the second cut-off drive current and reducing it, the cut-off surge voltage of the output voltage can be reduced. Since the cut-off surge voltage can be reduced, the first cut-off drive current can be increased compared to the case where the present invention is not implemented, the cut-off switch of the power semiconductor element 20 can be made faster, and the switching loss during the cut-off can be reduced.

[0073] On the other hand, when the PWM gate drive signal 11 is a conduction command, the gate drive current at the time of the conduction is stopped by switching the conduction control switch 78 to the conduction reference voltage 70 side and the negative feedback operation of the conduction control amplifier 77. In addition, the conduction control switch 74 is switched from the power supply voltage VCC8 to the conduction control reference voltage 75, and the conduction control amplifier negative feedback terminal 72 is controlled to the same voltage as the conduction control reference voltage 75 by the negative feedback operation of the conduction control amplifier 73, thereby allowing the gate drive current on the conduction side to flow.

[0074] Here, when the conduction operation starts, the conduction current switching switch 63 is turned off, and the conduction current switching switch 83 is turned on. Figure 5 The first on-drive current shown is a current value obtained by dividing the on-control reference voltage 75 by the resistance values ​​of the resistors 64 and 65 .

[0075] As the gate drive for conduction begins, the power semiconductor element 20 begins to conduct, and the output voltage decreases. Figure 5 As shown, the reduction in output voltage is transmitted as a voltage reduction of the output detection terminal 42 via the capacitor 50. The delay time Don is adjusted by the resistor 56 and the capacitor 58, and the delay time Don is used to switch the signal to the second on-drive current. In addition, the resistor 56 and the capacitor 58 also act as a filter for preventing the noise of the output voltage from being erroneously detected.

[0076] When the input voltage is lower than the conduction detection reference voltage 60, the conduction detection comparator 62 detects the decrease in the output voltage, switches the conduction current switching switch 63 from off to on, and switches the conduction current switching switch 83 from on to off. As a result, the gate drive current at the time of conduction is switched to the second conduction drive current obtained by dividing the conduction control reference voltage 75 by the resistance value of the resistors 64 and 65.

[0077] In this embodiment, a method of switching the first and second on drive currents and the first and second off drive currents by switching the respective negative feedback terminals of the on control amplifier 73 and the off control amplifier 77 is described.

[0078] As another means, the drive current can be switched by switching the conduction control reference voltage 75 and the cutoff control reference voltage 81 separately, but the amplifier has a limited signal band and requires time for current switching. In the case where high-speed switching of the power semiconductor element 20 is not required, the configuration of switching the conduction control reference voltage 75 and the cutoff control reference voltage 81 separately is a simpler configuration and is more effective.

[0079] As described above, by increasing the gate drive current after the recovery surge voltage generated in the recovery operation of the freewheeling diode 21 of the arm is generated, the switching of the output voltage can be accelerated without increasing the recovery surge voltage, thereby reducing the on-switching loss. Embodiment 3

[0080] Reference Figure 3 An electronic control device and a gate driving method of a power semiconductor element according to a third embodiment of the present invention are described.

[0081] Figure 3 1 is a schematic diagram of the electronic control device of this embodiment, mainly showing the structure of the gate drive circuit 3. Figure 3 The gate drive circuit 3 shown is the same as the constant current drive mode in the second embodiment, and the switching method of the first on-driving current and the second on-driving current and the first off-driving current and the second off-driving current is different from that in the second embodiment. Figure 2 )same.

[0082] Similar to the second embodiment, the cut-off detection comparator 61 detects the increase in the output voltage of the power semiconductor element 20 at the time of cut-off, and switches the cut-off current switching switch 95 from on to off. Thus, the first cut-off drive current obtained by dividing the cut-off control reference voltage 81 by the resistance value of the parallel resistor of the resistors 93 and 94 can be switched to the second cut-off drive current obtained by dividing the cut-off control reference voltage 81 by the resistance value of the resistor 93.

[0083] On the other hand, similarly, when conducting, the conduction detection comparator 62 detects a decrease in the output voltage of the power semiconductor element 20, and switches the conduction current switching switch 92 from off to on. Thus, it is possible to switch from a first conduction drive current obtained by dividing the conduction control reference voltage 75 by the resistance value of the resistor 90 to a second conduction drive current obtained by dividing the conduction control reference voltage 75 by the resistance value of the parallel resistor of the resistors 90 and 91.

[0084] This embodiment is different from the second embodiment in that the negative feedback terminal of the amplifier is switched, and the negative feedback loop is not switched, so it is easy to obtain the stability of the amplifier. Embodiment 4

[0085] Reference Figure 6 An electronic control device and a gate driving method of a power semiconductor element according to a fourth embodiment of the present invention are described.

[0086] Figure 6 1 is a schematic diagram of the electronic control device of this embodiment, mainly showing the structure of the gate drive circuit 6. This embodiment is an embodiment in which the present invention is applied to a gate drive circuit of a constant voltage drive method.

[0087] In the constant voltage drive method, the PMOS FET 105 connected to the power supply voltage VCC8 is turned on, and the gate drive current at the time of on flows by the difference voltage between the power supply voltage VCC8 and the gate terminal 24 and the resistor 101. Similarly, the gate drive current at the time of off flows by the difference voltage between the gate terminal 24 and the off reference voltage 70 and the resistor 102 by turning on the NMOS FET 106. In this way, the gate drive can be performed by a simple structure of connecting the MOS FET to the gate terminal 24 via the resistor to turn it on and off, so it is generally widely used.

[0088] In this embodiment, when the PWM gate drive signal 11 output from the microcomputer 10 is a turn-off instruction, the inter-insulation communication unit 12 transmits a signal to turn off the PMOS FET 105 through the inverter 109. In addition, the PMOSFET 104 is similarly turned off through the NAND 108. As a result, the gate drive current flowing through the PMOS FET 105 and the PMOS FET 104 during the conduction is cut off.

[0089] Thereafter, the NMOS FET 106 connected to the inverter 109 is turned on, and similarly, the NMOS FET 107 is turned on through the AND 110. As a result, the first off-drive current starts to flow, and the off operation of the power semiconductor element 20 starts.

[0090] The operation from the start of the cut-off operation of the power semiconductor element 20 to the cut-off detection comparator 61 is the same as the operation described in the second and third embodiments. When the cut-off detection comparator 61 detects the increase in the output voltage of the power semiconductor element 20, the NMOS FET 107 is turned off through the inverter 111 and AND 110, so that the cut-off drive current is reduced and switched to the second cut-off drive current.

[0091] Thus, even in the constant voltage driving mode, the gate driving current can be reduced from the first cut-off driving current to the second cut-off driving current, similar to the constant current driving mode, so that the cut-off surge voltage of the output voltage can be reduced. Thus, compared with the case where the present invention is not implemented, the first cut-off driving current can be increased, the cut-off switch of the power semiconductor element 20 can be made faster, and the switching loss at the time of cut-off can be reduced.

[0092] When the PWM gate drive signal 11 is an on command, first, the NMOS FET 106 and the NMOS FET 107 are turned off. Then, the PMOS FET 105 is turned on, and a first on drive current determined by the voltage difference between the power supply voltage VCC8 and the gate terminal 24 and the resistor 101 flows, and the power semiconductor element 20 starts the on operation.

[0093] The operation from the turn-on operation of the power semiconductor element 20 to the conduction detection comparator 62 is the same as the operation described in the second and third embodiments. When the reduction in the output voltage of the power semiconductor element 20 is detected by the conduction detection comparator 62, the PMOS FET 104 is turned on through the NAND 108, and in addition to the first conduction drive current, the current from the PMOS FET 104 is also increased, and the second conduction drive current flows. In this way, even in the constant voltage drive mode, the same as the constant current drive mode, by increasing the gate drive current from the first conduction drive current to the second conduction drive current, the switching loss at the time of conduction can be reduced without increasing the recovery surge voltage to the arm. Embodiment 5

[0094] Reference Figure 7 An electronic control device according to a fifth embodiment of the present invention will be described.

[0095] Figure 7 This is a diagram showing a schematic configuration of an electronic control device according to the present embodiment, and shows an example of an inverter equipped with the gate drive circuit described in any one of the first to fourth embodiments.

[0096] like Figure 7 As shown, the electronic control device of this embodiment is an inverter 126 that converts DC power from a high-voltage battery 120 into three-phase AC power and supplies the power to a motor 121 for drive control.

[0097] Taking the W phase as an example, the power semiconductor element 20B and the flywheel diode 21B constituting the upper arm and the power semiconductor element 20A and the flywheel diode 21A constituting the lower arm are connected in series to form an arm of the W phase.

[0098] The power semiconductor element 20B and the power semiconductor element 20A are driven and controlled by gate drive currents generated by gate drive circuits 122B and 122A, respectively. The gate drive circuits 122B and 122A use the gate drive circuits described in any one of the first to fourth embodiments.

[0099] The gate drive circuits 122B and 122A generate gate drive currents according to on commands and off commands of the PWM gate drive signals 11B and 11A from the microcomputer 10, respectively, and input the gate drive currents to the power semiconductor element 20B and the power semiconductor element 20A.

[0100] The U phase and the V phase also form arms in the same manner as the W phase, and the inverter 126 is formed between the high-voltage battery 120 and the motor 121 in such a manner that the arms of the U phase, the V phase, and the W phase are connected in parallel.

[0101] A U-phase output terminal 125 , a V-phase output terminal 124 , and a W-phase output terminal 123 are respectively connected between upper and lower arms of the U-phase, V-phase, and W-phase, and are connected to the motor 121 .

[0102] The inverter 126 of the present embodiment is constructed as described above. The gate drive circuit of the present invention can reduce the switching loss of the power semiconductor element mounted inside, thereby improving the conversion efficiency of the inverter and increasing the maximum output power.

[0103] In addition, the present invention is not limited to the above-mentioned embodiments, and includes various modified examples. For example, the above-mentioned embodiments are embodiments described in detail in order to easily explain the present invention, and are not necessarily limited to embodiments having all the described structures. In addition, a part of the structure of one embodiment can be replaced with the structure of another embodiment, and the structure of one embodiment can be added to the structure of another embodiment. In addition, for a part of the structure of each embodiment, other structures can be added, deleted, or replaced. Explanation of symbols

[0104] 1, 2, 3, 6, 122A, 122B…gate drive circuit, 8…power supply voltage VCC, 10…microcontroller (microcomputer), 11, 11A, 11B…PWM gate drive signal, 12…inter-insulation communication unit, 20, 20A, 20B…power semiconductor element, 21, 21A, 21B…freewheeling diode, 22…drain terminal, 23…source terminal, 24…gate terminal, 30…gate on drive unit, 31…gate off drive unit, 32…on drive current switching unit, 33…off drive current switching unit, 40…output transmission unit, 41…constant voltage generating unit, 42…output detection terminal, 43…off filter adjustment unit Entire unit, 44…conduction filter adjustment unit, 45…output cutoff detection unit, 46…output conduction detection unit, 47, 82…cutoff detection signal, 48, 71…conduction detection signal, 50, 51, 57, 58…capacitor, 53, 55, 56…resistor, 54…constant voltage source, 59…reference voltage for cutoff detection, 60…reference voltage for conduction detection, 61…comparator for cutoff detection, 62…comparator for conduction detection, 63, 83, 92…switch for conduction current switching, 64, 65, 68, 69, 90, 91, 93, 94, 100, 101, 102, 103…resistor, 66, 104, 105…PMOS FET, 67, 106, 107…NMOS FET, 70…cutoff reference voltage, 72…conduction control amplifier negative feedback terminal, 73…conduction control amplifier, 74…conduction control switch, 75…conduction control reference voltage, 76, 109, 111…inverter, 77…cutoff control amplifier, 78…cutoff control switch, 79, 84, 95…cutoff current switching switch, 80…cutoff control amplifier negative feedback terminal, 81…cutoff control reference voltage, 108…NAND, 110…AND, 120…high-voltage battery, 121…motor, 123…W-phase output terminal, 124…V-phase output terminal, 125…U-phase output terminal, 126…inverter.

Claims

1. An electronic control device, characterized in that: have: Microcomputer; Power semiconductor components; and a gate drive circuit that generates a gate drive current for the power semiconductor element according to an instruction from the microcomputer, The gate drive circuit detects the start of the on and off action of the switch by detecting the change in the output voltage of the power semiconductor element. In the switch when it is turned on, the gate drive current is increased before reaching the peak voltage, In the switch at the off time, the gate drive current is reduced before the peak voltage is reached.

2. The electronic control device according to claim 1, characterized in that: The gate drive circuit has a capacitive coupling for detecting an output voltage of the power semiconductor element.

3. The electronic control device according to claim 1, characterized in that: The gate drive circuit includes a delay circuit for adjusting the timing from detection of the start of the on / off operation to increasing or decreasing the gate drive current.

4. The electronic control device according to claim 1, characterized in that: The gate driving circuit is a constant current driving mode or a constant voltage driving mode.

5. The electronic control device according to claim 1, characterized in that: The gate drive circuit detects the switch ON operation only once according to the ON command from the microcomputer, and latches the detection result until the next OFF command. The gate drive circuit detects the start of the switch OFF operation only once in response to the OFF command from the microcomputer, and latches the result of the detection until the next ON command is issued.

6. A gate driving method for a power semiconductor element, characterized in that: include: (a) a step of detecting the start of an operation of turning on or off a switch by detecting a change in voltage between a drain terminal and a source terminal of a power semiconductor element; (b) in a switch when the power semiconductor element is turned on, the step of increasing the gate drive current before reaching the peak voltage; as well as (c) A step of reducing a gate drive current before reaching a peak voltage in a switch when the power semiconductor element is turned off.

7. The gate driving method of a power semiconductor element according to claim 6, characterized in that: In the step (a), a change in voltage between the drain terminal and the source terminal of the power semiconductor element is detected using capacitive coupling.

8. The gate driving method of a power semiconductor element according to claim 6, characterized in that: In the step (b) or the step (c), the timing from the detection of the start of the on / off operation of the power semiconductor element to the increase / decrease of the gate drive current is delayed by a predetermined time.

9. The gate driving method of a power semiconductor element according to claim 6, characterized in that: It is either a constant current driving method in which a gate is driven with a constant current or a constant voltage driving method in which a gate driving current is generated by a driving voltage and a resistor.

10. The gate driving method of a power semiconductor element according to claim 6, characterized in that: According to the on-command from the microcomputer, the on-action of the switch is detected only once, and the result of the detection is latched until the next off-command. The start of the switch OFF operation is detected only once in response to an OFF command from the microcomputer, and the result of the detection is latched until the next ON command is given.

Images