87results about "Analogue/digital/analogue conversion" patented technology

The invention discloses a memristor-based signal detection circuit and method, a receiver and equipment, and relates to the field of wireless communication, a voltage source module of the circuit is connected with a voltage input end of a memristor array module, and a current source module is connected with a current input end of the memristor array module; the current output end of the memristor array module is connected with the reverse input end of the operational amplifier module and one end of the feedback resistor module, the other end of the feedback resistor module and the output end of the operational amplifier module are connected with the input end of the multiplier module, and the output end of the multiplier module is connected with one end of the resistor module. The voltage of the voltage source module is set according to the emission vector set; the current of the current source module is set according to the received radio frequency signal, and the conductance value of the memristor is set according to the channel matrix, so that a relatively low bit error rate of signal detection can be realized on the basis of greatly reducing calculation time and power consumption, and meanwhile, the requirement on programmable bit precision of the memristor is also reduced.

The various implementations described herein include techniques and apparatuses for multi-channel biopotential signal acquisition, biopotential signal pre-processing, and adaptive signal conditioning. In one aspect, an analog frontend circuit includes an instrumentation amplifier (INA) and an analog-to-digital circuit (ADC) in a forward signal path. A digital circuit receives input from the ADC. An adaptive baseline tracking and compensation circuit tracks and compensates moving motion artifact driven changes. A power line interference (PLI) detection and compensation circuit tracks a desired number of PLI harmonics, and magnitude, phase and frequency for the PLI harmonics in real time. A digital-to-analog converter (DAC) circuit combines output of the adaptive baseline tracking and compensation circuit and the PLI detection and compensation circuit to output an analog output. A passive filter receives the analog output and drives an analog compensation signal at an input of the INA.

According to an aspect of the present disclosure, a display device includes: a stretchable touch panel having a plurality of touch electrodes; a stretchable display panel configured to display an image; and a touch driver configured to operate the stretchable touch panel, in which the touch driver recognizes a stretchable area of the stretchable touch panel and corrects a touch data value of the stretchable area of the stretchable touch panel, thereby improving touch performance of the stretchable touch panel.

According to an aspect of the present disclosure, a display device includes: a stretchable touch panel having a plurality of touch electrodes; a stretchable display panel configured to display an image; and a touch driver configured to operate the stretchable touch panel, in which the touch driver recognizes a stretchable area of the stretchable touch panel and corrects a touch data value of the stretchable area of the stretchable touch panel, thereby improving touch performance of the stretchable touch panel.

The invention discloses an embedded special high-frequency low-level control system, which comprises a digital signal processing board card, an ADC / DAC sub-board card and a radio frequency front-end board card, the radio frequency front-end board card comprises two paths of up-conversion channels and six paths of down-conversion channels; the digital signal processing board card comprises an FPGA (Field Programmable Gate Array); wherein the radio frequency front-end board card is used for dividing an input reference line RF signal into four paths of RF reference signals and generating an LO signal; the ADC / DAC sub board card is used for ADC analog-to-digital conversion and DAC digital-to-analog conversion; the main functions of the digital signal processing board card comprise clock distribution of RF reference signals, a motor drive and piezo ceramic drive circuit, a data acquisition and logic control algorithm of an FPGA logic unit PL part, an embedded ARM system of an FPGA processor unit PS part, EPICS-IOC application of a low-level system, network data communication and the like.

The invention discloses a digital measurement system channel error automatic calibration method, a storage medium and a system, and aims to automatically calibrate zero drift and multiplying power change errors from the angle of reducing DMS analog measurement channel tool errors. The method comprises the following steps of: firstly, connecting an input end of the DMS with a digital-to-analog converter (DAC), a circuit ground and a reference source Vref respectively, then measuring corresponding output voltages Dos, Dx and Dref of the DMS, and finally obtaining a calibration voltage Ui after error elimination by utilizing a formula # imgabs0 #. The calibration circuit required by the invention is simple in structure, low in cost, suitable for different types of DMS equipment, free of synchronism requirements on a measurement system, low in operation difficulty, capable of calibrating relative errors and absolute errors, high in automation degree, and capable of improving the measurement precision of the DMS on the premise of considering the measurement time; and the working reliability and stability of the measuring equipment are improved.

The signal transmission device includes first, second and third chips. The first and second chips includes respectively: a first input pad; an ADC that converts a first analog signal inputted to the first input pad into a first digital signal; a first transmission circuit that generates a first pulse signal in correspondence to the first digital signal; a first output pad that outputs the first pulse signal; a second input pad; a first reception circuit that generates a second digital signal in correspondence to a second pulse signal inputted to the second input pad; a DAC that converts the second digital signal into a second analog signal; and a second output pad that outputs the second analog signal. The third chip, upon receiving the first pulse signal from the first output pad of the first chip, outputs the second pulse signal to the second input pad of the second chip.

The various implementations described herein include techniques and apparatuses for multi-channel biopotential signal acquisition, biopotential signal pre-processing, and adaptive signal conditioning. In one aspect, an analog frontend circuit includes an instrumentation amplifier (INA) and an analog-to-digital circuit (ADC) in a forward signal path. A digital circuit receives input from the ADC. An adaptive baseline tracking and compensation circuit tracks and compensates moving motion artifact driven changes. A power line interference (PLI) detection and compensation circuit tracks a desired number of PLI harmonics, and magnitude, phase and frequency for the PLI harmonics in real time. A digital-to-analog converter (DAC) circuit combines output of the adaptive baseline tracking and compensation circuit and the PLI detection and compensation circuit to output an analog output. A passive filter receives the analog output and drives an analog compensation signal at an input of the INA.

The invention provides a crystal oscillator taming system based on a temperature compensation chip, which comprises a crystal oscillator, the temperature compensation chip, a frequency dividing circuit, a phase measurement module, a microcontroller and a digital-to-analog converter, and is characterized in that the temperature compensation chip is used for performing temperature compensation on the crystal oscillator; the frequency dividing circuit is used for performing frequency dividing processing on an output signal of the crystal oscillator; the phase measurement module is used for measuring the phase difference between the frequency division signal and the reference signal; the microcontroller is used for storing and periodically updating frequency compensation values of the crystal oscillator at different temperatures; the processing module is also used for processing the phase difference based on a Kalman filtering algorithm when the reference signal is valid, and processing the filtered phase difference based on a PID control algorithm when the filtered phase difference is greater than or equal to a preset threshold value; the digital-to-analog converter is used for converting the adjusted phase difference into an analog signal. The invention provides a crystal oscillator taming system based on a temperature compensation chip. The system is used for solving the problem that in the prior art, temperature compensation only depends on the temperature compensation chip, and the occasion with the high frequency precision requirement cannot be met.

The integrated circuit (100A) includes an H-bridge circuit (102) having a first output node (OUT1) for coupling to a high-side terminal of an inductor (103) and a second output node (OUT2) for coupling to a low-side terminal of the inductor. A current sense FET (SNS-DRV) is coupled between a current source (110) and a lower supply voltage to provide a reference current (Itrip) including a peak current limit at the sense node. A current sense comparator (104) has a first input coupled to the sense node, a second input coupled to a second output node, and an output (113) coupled to send an output signal to a driver control circuit. A FET linear detection circuit (112) is coupled to receive a gate voltage (LS2) of an active low-side power FET (Mls2) and has an output (CMP_EN) coupled to enable the current sense comparator when the active low-side power FET is operating in its linear region.

The invention provides a linear frequency modulation signal generation method and device based on multi-path parallel real-time calculation, and relates to the technical field of synthetic aperture radars. Comprising the following steps: determining an initial frequency control word and a frequency modulation slope control word according to a preset linear frequency modulation signal parameter; generating k parallel frequency control words based on the constructed virtual serial frequency control word, the initial frequency control word and the frequency modulation slope control word, wherein k is an integer greater than 1; respectively inputting the k paths of parallel frequency control words into k phase accumulators, and synchronously generating k paths of linear frequency modulation signals with continuous phases; and the k paths of signals are combined and output as broadband linear frequency modulation signals through a digital-to-analog converter. On the basis of arithmetic progression characteristics of virtual serial frequency control words, phase compensation terms of all parallel branches are eliminated, and phase continuity among multiple signals is guaranteed through synchronous recursion of multiple phase accumulators.

The invention discloses a special high-frequency low-level control system, which is characterized by comprising a digital signal processing board card and a radio frequency front-end board card, the digital signal processing board card mainly comprises a clock distribution unit, an ADC digital-to-analog conversion unit, a DAC analog-to-digital conversion unit, an FPGA and a cavity frequency tuning driving unit. The ADC digital-to-analog conversion unit is used for converting an intermediate frequency acquisition analog signal output by the radio frequency front-end board card into a digital intermediate frequency signal and sending the digital intermediate frequency signal to the FPGA; the DAC analog-to-digital conversion unit is used for converting the DDS excitation signal output by the FPGA into an intermediate frequency excitation analog signal and sending the intermediate frequency excitation analog signal to the radio frequency front-end The radio frequency front-end board card performs up-conversion on the intermediate-frequency excitation analog signal to obtain an RF excitation signal, sends the RF excitation signal to a high-frequency cavity for field construction, and performs down-conversion on a cavity field recovery signal to obtain an intermediate-frequency acquisition analog signal; the cavity frequency tuning drive unit comprises a motor slow tuning drive and a piezoelectric ceramic fast tuning drive; and the FPGA is used for data acquisition and loop control.

An integrated circuit (100A) includes an H-bridge circuit (102) having a first output node (OUT1) for coupling to the high-side terminal of an inductor (103) and a second output node (OUT2) for coupling to the low-side terminal of the inductor. A current-sensing FET (SNS-DRV) is coupled between a current source (110) and a lower supply voltage to provide a reference current (Itrip), including a peak current limit at the sensing node. A current-sensing comparator (104) has a first input coupled to the sensing node, a second input coupled to the second output node, and an output (113) coupled to send an output signal to a driver control circuit. A FET linearity detection circuit (112) is coupled to receive the gate voltage (LS2) of an active low-side power FET (Mls2) and has an output (CMP EN) coupled to enable the current-sensing comparator when the active low-side power FET operates in the linear region.

An ADC circuit includes an ADC that converts an input analog signal to a digital signal. The ADC circuit includes a filter circuit that receives the analog input signal and provides a filtered signal to a combiner circuit. The ADC circuit includes a DAC that converts the digital signal back to an analog signal that is provided to a combiner circuit. The DAC includes one or more capacitive paths with capacitors between the input of the DAC and the output of the DAC.

The present invention relates to a wireless microphone system with which a receiver user can transmit sound to a wireless microphone user and with which the sound of the receiver user can be recorded, without a separate communication means or recording means.

The application discloses a signal detection circuit and method based on a memristor, a receiver and equipment, and relates to the field of wireless communication. A voltage source module of the circuit is connected with a voltage input end of a memristor array module, a current source module is connected with a current input end of the memristor array module, a current output end of the memristor array module is connected with an inverting input end of an operational amplifier module and one end of a feedback resistance module respectively, the other end of the feedback resistance module and an output end of the operational amplifier module are connected with an input end of a multiplier module, and an output end of the multiplier module is connected with one end of a resistance module. The voltage of the voltage source module is set according to a set of transmission vectors, the current of the current source module is set according to a received radio frequency signal, and the conductance value of the memristor is set according to a channel matrix. The application can realize a lower bit error rate of signal detection on the basis of greatly reducing the calculation time and power consumption, and also reduces the requirement for the programmable bit precision of the memristor.

An apparatus to monitor and optimise power output by one or more solar panels to which the apparatus is coupled comprises a processor configured to generate a periodic wave and apply the periodic wave to an output of the one or more solar panels. Analogue-to-digital voltage and current converters receive voltage and current signals respectively from the one or more solar panels and provide digital voltage and current signals to the processor. The processor is configured to: calculate a voltage amplitude and a direct current offset of the periodic wave applied to the output of the one or more solar panels; calculate a differential of a power and a voltage of the one or more solar panels based on the voltage amplitude and the direct current offset; and modify the voltage of the one or more solar panels such that the differential of the power and the voltage of the one or more solar panels is zero, or substantially zero.

A method for calibrating analog-to-digital conversion includes converting, by an analog-to-digital converter (ADC), a first input voltage to a first digital code. The first input voltage is generated from a reference voltage used as a reference voltage by the ADC. The method includes converting, by the ADC, a second input voltage to a second digital code. The second input voltage is generated from the reference voltage used as the reference voltage by the ADC. The method also includes calculating a calibration factor based on the first digital code, the second digital code, the first input voltage, and the second input voltage, converting, by the ADC, a third voltage to a third digital code, and correcting the third digital code using the calibration factor.

Systems and methods for power efficient successive approximation analog-to-digital converters (SAR ADCs) are disclosed herein. In one aspect, the SAR ADC includes a sampling and digital-to-analog conversion (DAC) circuit to sample an input voltage. In one aspect, the SAR ADC includes a first comparator coupled to the DAC circuit, and a first set of memory circuits coupled between the first comparator and the DAC circuit. In one aspect, the SAR ADC includes a second comparator coupled to the DAC circuit, and a second set of memory circuits coupled between the second comparator and the DAC circuit. In one aspect, the SAR ADC includes a control circuit configured to select, for each of a plurality of bits corresponding to the input voltage, a corresponding comparator to determine a state of the each of the plurality of bits during a corresponding time period.

Residual value generation system for use in a continuous-time stage of an analog-to-digital converter (ADC), wherein the system comprises: a forward path; a feedforward path comprising a quantizer; and one or more stub line filters at an input to the forward path and the quantizer.

The invention discloses an eight-channel input and output data acquisition device which comprises an analog signal input interface, a first signal conditioning module, an A / D conversion module, an EMIF circuit, a DSP processing module, an SPI output circuit, a D / A conversion module, a second signal conditioning module and an analog output interface. The analog signal input interface receives analog signals of eight channels, the analog signals are filtered by the first signal conditioning module and then are transmitted to the A / D conversion module through the EMIF circuit, the A / D conversion module carries out analog-to-digital conversion, digital signals are transmitted to the DSP processing module through the EMIF circuit, the DSP processing module processes the digital signals, and the digital signals are transmitted to the analog-to-digital conversion module through the EMIF circuit. The processed eight-channel digital signal is transmitted to a D / A conversion module through an SPI output circuit, the D / A conversion module performs analog-to-digital conversion, and an analog signal is amplified and subjected to low-pass filtering through a second signal conditioning module and then is output to an analog output interface; high-speed data processing and analysis are achieved, the real-time requirement is met, a built-in FPGA is not needed, development and debugging are easy, and the development and maintenance cost is reduced.

The phono preamplifier, which processes the audio output signal from the turntable, is powered by a variable voltage adapter, such as a USB-C to PD power adapter.

Disclosed herein is a system and method for optimizing audio equalization settings based on the type of music being broadcast, comprising: receiving audio at a processing device; performing a frequency analysis of the received audio, to determine a plurality of frequency components and associated amplitudes of the frequency components of the received audio; generating a spectral plot of the received audio based on the performed frequency analysis of the received audio, wherein the spectral plot comprises an x axis that represents relative amplitude and a y axis that represents frequency components of the received audio; comparing the spectral plot of the received audio to each of a plurality of different predetermined spectral plots; matching the spectral plot of the received audio to at least one of a plurality of different predetermined spectral plots; retrieving a predetermined equalizer settings file that corresponds to the at least one of the matched predetermined spectral plots, wherein the predetermined equalizer settings file comprises a plurality of relative amplitude settings for each of a plurality of frequency bands; and applying the retrieved predetermined equalizer settings to an equalizer that processes the received audio according to the predetermined equalizer settings in the predetermined equalizer settings file.

Disclosed herein are related to systems and methods for a power efficient successive approximation analog to digital converter (SAR ADC). In one aspect, the SAR ADC includes a sample and digital to analog conversion (DAC) circuit to sample an input voltage. In one aspect, the SAR ADC includes a first comparator coupled to the DAC circuit, and a first set of storage circuits coupled between the first comparator and the DAC circuit. In one aspect, the SAR ADC includes a second comparator coupled to the DAC circuit, and a second set of storage circuits coupled between the second comparator and the DAC circuit. In one aspect, the SAR ADC includes a control circuit configured to select, for each of multiple bits corresponding to the input voltage, a corresponding comparator to determine a state of the each of the multiple bits during a corresponding time period.

The present invention relates to the control of semiconductor devices, in particular MOS devices, in order to reduce RTS / flicker noise. A circuit (100) comprises a first MOS device (103, 104) and a bias controller (107). The circuit is capable of at least one first circuit state (P RO ) and the second circuit state (P RST ) operation, in the first circuit state, the first MOS device is active to contribute to a first signal (Sout), and in the second circuit state, the first MOS device does not contribute to the first signal. The bias controller is operable to control the voltage at one or more terminals of the first MOS device to apply a pre-bias voltage (Vout) during instances of the second circuit state. PB1 、V PB2 ). The pre-bias is applied to set an occupied state of charge carrier traps within the first MOS device to limit noise during subsequent operation in the first circuit state. In an embodiment, the bias controller is configured such that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.

An ADC circuit includes an ADC that converts an input analog signal to a digital signal. The ADC circuit includes a filter circuit that receives the analog input signal and provides a filtered signal to a combiner circuit. The ADC circuit includes a DAC that converts the digital signal back to an analog signal that is provided to a combiner circuit. The DAC includes one or more capacitive paths with capacitors between the input of the DAC and the output of the DAC.

The reference voltage generator (200) includes a comparator (225), a digital-to-analog converter (DAC) (255), and a switched capacitor accumulator (160). The comparator receives a reference voltage input (144), a feedback input (195), and a control signal (148). The DAC is coupled to the output of the comparator, and the switched capacitor accumulator is coupled to the output of the DAC. In some implementations, a digital filter is coupled between the output of the comparator and the input of the DAC. The switched capacitor accumulator may be coupled to a buffer (170) that outputs the feedback input and a reference voltage (130) for an analog-to-digital converter (ADC). In some implementations, the feedback loop includes N 1-bit DACs coupled to the output of the comparator, and N switched capacitor accumulators, each coupled to a unique 1-bit DAC.

A system and method are described herein for configuring an audio distribution system, comprising a Redis server, the Redis server adapted to store Redis data to be used in configuring the audio distribution system; a plurality of audio devices, the plurality of audio devices and Redis server interconnected to form the audio distribution system, wherein each of the plurality of audio devices comprises—at least one processor; an electronic communications interface operatively connected to the at least one processor and adapted to receive data from a user and transfer the data to the at least one processor; and a memory operatively connected with the at least one processor, wherein the memory stores computer-executable instructions that, when executed by the at least one processor, causes the at least one processor in a first audio device to execute a method for configuring the audio distribution system that comprises: establishing communications using the electronic communications interface between the user and the at least one processor of the first audio device, such that data input by the user is received by the at least one processor of the first audio device; establishing communications to each of the remaining plurality of audio devices and Redis server in the audio distribution system; obtaining information from each of the remaining plurality of audio devices with which communications have been established, such information including one or more of an audio device name, part number, serial number, internet protocol address number, and physical location; receiving configuration information from the user that pertains to a specific audio device of the plurality of audio devices in the audio distribution system that, when installed on a specific audio device, causes the specific audio device to operate in a known manner; and copying that configuration information to others of the same specific type of audio device in the audio distribution system.

The invention belongs to the field of aviation electromechanical atmosphere data systems, and particularly relates to an STM32-based temperature compensation amplification circuit and a use method. A single-chip microcomputer or a DSP is often used for converting pressure into digital quantity, the digital quantity is converted into analog quantity through an external DA converter, temperature compensation is avoided, and errors are usually large. According to the invention, a two-dimensional array of voltage VTempp-digital quantity Code-analog quantity of a temperature measurement module is stored in an EEPROM (Electrically Erasable Programmable Read-Only Memory); a pressure signal P is converted into a frequency signal f through the pressure measuring module and sent to the timer, the frequency signal f is sent to the resolving module after being converted by the timer, the resolving module obtains a temperature compensation signal by inquiring a two-dimensional array and through interpolation, and a compensated digital signal is sent to the operational amplifier circuit through the D / A converter. The digital quantity temperature compensation of the analog amplification circuit can be realized, the whole product can meet the + / -20mV analog quantity output requirement in the full temperature range, the problem of large output error of two DAs in the full temperature range of the product is solved, and the circuit is simple and low in cost.

An example system includes a plurality of network nodes, each network node including one or more respective first transceivers and one or more respective second transceivers, the first transceivers being configured to transmit data according to a first maximum throughput, and the second transceivers being configured to transmit data according to a second maximum throughput that is less than the first maximum throughput. The first network node is configured to transmit, using a respective one of the first transceivers, first data comprising a plurality of optical subcarriers to two or more second network nodes according to the first maximum throughput, each optical subcarrier being associated with a different one of two other network nodes. The two or more second network nodes are configured to receive the first data from the first network node using respective ones of the second transceivers.