12-bit high speed streamline analog-to-digital converter with background calibration function

Abstract

The invention discloses a 12-bit high speed streamline analog-to-digital converter with a background calibration function. The 12-bit high speed streamline analog-to-digital converter with a background calibration function utilizes a sample hold circuit structure without a front end and the whole streamline has five levels, wherein the first streamline level is 3.5-bit; the second streamline level to the fourth streamline level are 2.5-bit; and the fifth streamline level is 3-bit flash ADC. The 12-bit high speed streamline analog-to-digital converter with a background calibration function is featured in that in the streamline, the first streamline level utilizes a 3.5-bit MDAC structure with overflow bit and is integrated with a sampling time deviation calibration module which is used for realizing correction of the sampling time deviation of two sampling networks including an MDAC and a sub ADC; besides, the analog-to-digital converter also includes a reference voltage generation circuit which is used for providing stable reference voltage for each streamline level, a clock generation circuit which is used for providing a accurate clock for each streamline level, and a redundancy correction circuit for misalignment addition of output coding. The 12-bit high speed streamline analog-to-digital converter with a background calibration function of the invention has the advantages of being low in power consumption, and being able to realize high speed application when the process size is small.

Description

technical field [0001] The invention relates to an analog-to-digital converter, in particular to a 12-bit high-speed assembly line analog-to-digital converter with background calibration, and belongs to the technical field of wireless communication. Background technique [0002] With the continuous innovation of wireless communication technology, wireless communication equipment puts forward more stringent requirements on the performance of analog-to-digital converter (ADC). The ADC must also have good intermediate frequency sampling performance while meeting high-speed and high-precision requirements. Pipeline ADC has a good compromise in terms of speed, precision and power consumption, so it is widely used in high-speed and high-precision occasions. In RF applications, for RF sampling ADCs, the sampling rate has reached GHz or higher, which is difficult to achieve for pipeline ADCs, so in many cases a band-pass sampling structure is used, and the band-pass sampling theore...

AI Technical Summary

Problems solved by technology

But it is very difficult to achieve these precise matches, and considering the changes in PVTL (process, power supply voltage, temperature, load) in practice, the ADC can still only achieve the pre-designed results under certain conditions, which greatly limits designed application

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