Successive approximation type analog-to-digital converter and calibration method

Abstract

The invention provides a successive approximation type analog-to-digital converter and a calibration method. The successive approximation type analog-to-digital converter comprises a sampling / holdingcircuit, a digital-to-analog converter, a comparator, a successive approximation logic circuit, a clock generation circuit and a digital pseudo-random signal generator. An analog input signal is connected to the sampling / holding circuit. Positive and negative input ends of the comparator are connected with the digital-analog converter and the sampling / holding circuit respectively, and the output end of the comparator is connected with the successive approximation logic circuit; the successive approximation logic circuit and the digital pseudo-random signal generator are connected to the inputof the adder, and the output of the adder is connected with the digital-to-analog converter; the successive approximation logic circuit and the digital pseudo-random signal generator are connected tothe input of a subtracter, and the output of the subtracter is a final output result; and the clock generation circuit is respectively connected with the comparator and the successive approximation logic circuit. Harmonic energy is reduced, the spurious-free dynamic range of the ADC is improved, and the linearity of the core ADC is effectively improved.

Description

technical field [0001] The invention relates to the technical field of mixed signal circuits, in particular to a successive approximation analog-to-digital converter and a calibration method. Background technique [0002] In the communication circuit, the analog-to-digital converter (ADC) is a very important module, which is responsible for converting the analog signal received by the radio frequency front end (RFFE) into a digital signal and providing it to the digital processor (DSP) for processing. In the development process of the receiver architecture, due to the increasingly simplified design of the RF front-end and the faster and more powerful digital processor functions, the performance of the ADC has increasingly become a bottleneck restricting the performance of the receiver. The indicators to measure the analog-to-digital converter mainly include bandwidth (speed), precision and power consumption. [0003] The successive approximation (SAR) analog-to-digital conv...

AI Technical Summary

Problems solved by technology

A linear improved sampling switch with parasitic capacitance compensation is disclosed in the prior art, which keeps the parasitic capacitance of the sampling switch basically constant with the change of the input signal, and improves the matching of the differential sampling switch; also discloses another capacitive digital-to-analog conversion The linear correction algorithm of the amplifier (CDAC), since the capacitance weight error is expressed as the difference between the actual weight and the ideal weight relative to the standard size, the calibrated CDAC digital representation has no gain error

Images